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Bused Hypercubes and Other Pin-Optimal Networks
January 1992 (vol. 3 no. 1)
pp. 14-24
ASCII Text
x 
 
C.M. Fiduccia, "Bused Hypercubes and Other Pin-Optimal Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 1, pp. 14-24, January, 1992.
 
 
BibTex
x
 
@article{ 10.1109/71.113079,
author = {C.M. Fiduccia},
title = {Bused Hypercubes and Other Pin-Optimal Networks},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {3},
number = {1},
issn = {1045-9219},
year = {1992},
pages = {14-24},
doi = {http://doi.ieeecomputersociety.org/10.1109/71.113079},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Bused Hypercubes and Other Pin-Optimal Networks
IS - 1
SN - 1045-9219
SP14
EP24
EPD - 14-24
A1 - C.M. Fiduccia,
PY - 1992
KW - Index Termspin minimisation; simultaneous data exchange; pin-optimal networks; massively parallelarchitectures; processing elements; chip; board; chassis; bused hypercubeinterconnection network; clock tick; ports; hypercube networks
VL - 3
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 
Pin minimization is an important issue for massively parallel architectures because the number of processing elements that can be placed on a chip, board, or chassis is often pin limited. A d-dimensional bused hypercube interconnection network is presented that allows nodes to simultaneously (in one clock tick) exchange data across any dimension using only d+1 ports per node rather than 2d. Despite this near two-to-one reduction, the network also allows nodes that are two dimensions apart to simultaneously exchange data; as a result, certain routings can be performed in nearly half the time. The network is shown to be a special case of a general construction in which any set of d permutations can be performed, in one clock tick, using only d+1 ports per node. A lower-bound technique is also presented and used to establish the optimality of the network, as well as that of several other new bused networks.

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Index Terms:
Index Termspin minimisation; simultaneous data exchange; pin-optimal networks; massively parallelarchitectures; processing elements; chip; board; chassis; bused hypercubeinterconnection network; clock tick; ports; hypercube networks
Citation:
C.M. Fiduccia, "Bused Hypercubes and Other Pin-Optimal Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 1, pp. 14-24, Jan. 1992, doi:10.1109/71.113079
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