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Bused Hypercubes and Other Pin-Optimal Networks
January 1992 (vol. 3 no. 1)
pp. 14-24
Pin minimization is an important issue for massively parallel architectures because the number of processing elements that can be placed on a chip, board, or chassis is often pin limited. A d-dimensional bused hypercube interconnection network is presented that allows nodes to simultaneously (in one clock tick) exchange data across any dimension using only d+1 ports per node rather than 2d. Despite this near two-to-one reduction, the network also allows nodes that are two dimensions apart to simultaneously exchange data; as a result, certain routings can be performed in nearly half the time. The network is shown to be a special case of a general construction in which any set of d permutations can be performed, in one clock tick, using only d+1 ports per node. A lower-bound technique is also presented and used to establish the optimality of the network, as well as that of several other new bused networks.

[1] J. C. Bermond, J. Bond, and J. F. Sacle, "Large hypergraphs of diameter 1," inGraph Theory and Combinatorics, B. Bollobas, Ed. London, England: Academic, 1984.
[2] C. M. Fiduccia, "Local interconnection scheme for parallel processing architectures," U.S. Patent 4739476, Apr. 1988.
[3] C. M. Fiduccia, "A bussed hypercube and other optimal permutation networks," GE Res. Develop. Center, Rep. 88CRD255, presented at the Fourth SIAM Conf. Discrete Math., San Francisco, CA, June 1988.
[4] F. Harary,Graph Theory. Reading, MA: Addison-Wesley, 1972.
[5] J. Kilian, S. Kipnis, and C. E. Leiserson, "The organization of permutation architectures with bussed interconnections," inProc. 28th Annu. Symp. Foundations Comput. Sci., IEEE, Oct. 1987.
[6] E. S. Lander,Symmetric Designs: An Algebraic Approach. New York: Cambridge University Press, 1983.
[7] M.D. Mickunas, "Using projective geometry to design bus connection networks," inProc. Workshop Interconnection Networks for Parallel and Distributed Processing, ACM/IEEE, Apr. 1980.
[8] F. P. Preparata and J. Vuillemin, "The cube-connected cycle: A versatile network for parallel computation,"Commun. ACM, vol. 24, pp. 300-309, May 1981.
[9] H. J. Siegel,Interconnection Networks for Large-Scale Parallel Processing: Theory and Case Studies. Lexington, MA: Lexington Books, 1985.
[10] C.L. Wu and T.Y. Feng,Interconnection Networks for Parallel and Distributed Processing, Computer Society Press, Los Alamitos, Calif., Order No. 574, 1984.

Index Terms:
Index Termspin minimisation; simultaneous data exchange; pin-optimal networks; massively parallelarchitectures; processing elements; chip; board; chassis; bused hypercubeinterconnection network; clock tick; ports; hypercube networks
C.M. Fiduccia, "Bused Hypercubes and Other Pin-Optimal Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 1, pp. 14-24, Jan. 1992, doi:10.1109/71.113079
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