
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
J.L. Aravena, A.O. Barbir, "A Class of Low Complexity High Concurrence Algorithms," IEEE Transactions on Parallel and Distributed Systems, vol. 2, no. 4, pp. 495502, October, 1991.  
BibTex  x  
@article{ 10.1109/71.97905, author = {J.L. Aravena and A.O. Barbir}, title = {A Class of Low Complexity High Concurrence Algorithms}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {2}, number = {4}, issn = {10459219}, year = {1991}, pages = {495502}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.97905}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Parallel and Distributed Systems TI  A Class of Low Complexity High Concurrence Algorithms IS  4 SN  10459219 SP495 EP502 EPD  495502 A1  J.L. Aravena, A1  A.O. Barbir, PY  1991 KW  Index Termstransformations families; low complexity high concurrence algorithms; dedicatedcomputing structures; compute cycles; design parameter; architecture; matrixmultiplication array; realtime applications; least square approximation; computationalcomplexity; least squares approximations; matrix algebra; parallel algorithms VL  2 JA  IEEE Transactions on Parallel and Distributed Systems ER   
A nonconventional approach to the analysis of dedicated computing structures in which the number of compute cycles is used as a design parameter to determine families of transformations implementable in the structure is presented. Using this approach, a single architecture can be used to implement a family of transformations with varying degrees of complexity. The transformations generated by a matrix multiplication array are considered in detail. It is shown that, for some realtime applications it becomes possible to incorporate the compute time as a constraint for designs based in optimality criteria. In particular, a least square approximation problem is discussed.
[1] A. Karatsuba and Yu. Ofman, "Multiplication of multidigit numbers on automata,"Soviet Physics Dokl., vol. 7, pp. 595596, 1963.
[2] V. Strassen, "Gaussian elimination is not optimal,"Number Math., vol. 13, pp. 354356, 1969.
[3] J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series,"Math. Comp., vol. 19, pp. 297301, 1965.
[4] R. W. Brockett, and D. Dobkin, "On the optimal evaluation of a set of bilinear forms," inProc. 5th Annu. ACM Symp. Theory Comput., 1973, pp. 8895.
[5] S. Winograd, "Arithmetic complexity of computations,"CBMS, vol. 33, SIAM, 1980.
[6] H. F. deGroote, "Lectures on the complexity of bilinear problems," inLecture Notes in Computer Science, vol. 245. Berlin, Germany: SpringerVerlag, 1987.
[7] R. E. Blahut,Fast Algorithms for Digital Signal Processing. Reading: MA: AddisonWesley, 1985.
[8] J. L. Aravena, "Triple matrix product architectures for fast signal processing,"IEEE Trans. Circuit Syst., vol. 35, no. 1, pp. 119122, Jan. 1988.
[9] J. L. Aravena, and W. A. Porter, "Array based design of digital filters,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP38, no. 9, pp. 16281632, Sept. 1990.
[10] J. L. Aravena, "Systematic design of fast discrete controllers," inAdvances in Computing and Control, Lecture Notes in Control and Information Sciences, vol. 130. Heidelberg, Germany: SpringerVerlag, 1989, pp. 128138.
[11] J. L. Aravena and W. A. Porter, "Nonplanar switchable arrays,"J. Cont. Syst. Sig. Proc., vol. 7, no. 2, pp. 213234, 1988.
[12] W. A. Porter, "An overview of polynomic system theory,"Proc. IEEE, Special Issue on System Theory, Jan. 1976.
[13] A. O. Barbir, "Systolic array implementations with reduced compute time," Ph.D. dissertation, Louisiana State Univ., Baton Rouge, LA, 1989.
[14] W. A. Porter, "Computational aspects of quadratic signal processing,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP38, no. 1, pp. 137144, Jan. 1990.
[15] H. T. Kung, "Why systolic architectures?,"IEEE Comput. Mag., vol. 15, no. 1, pp. 3746, 1982.
[16] S.Y. Kung, "VLSI Array Processors,"IEEE ASSP Magazine, Vol. 2, No. 3, July 1985, pp. 422.
[17] H. G. Yeh, "Systolic implementation of Kalman filtering,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP35, no. 9, pp. 15141517, Sept. 1987.
[18] S. Y. Kung, "Mapping digital signal processing algorithms onto VLSI systolic/wavefront arrays," inProc. 20th Asilomar Conf. Sig., Syst.,&Comp., 1986, pp. 611.
[19] H. K. Kwan and T. S. OkulloOballa, "2D systolic arrays for realization of 2D convolution,"IEEE Trans. Circuit Syst., vol. CAS37, no. 2, pp. 267272, Feb. 1990.