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| K. Padmanabhan, "Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors," IEEE Transactions on Parallel and Distributed Systems, vol. 2, no. 4, pp. 385-397, October, 1991. | |||
| BibTex | x | ||
| @article{ 10.1109/71.97896, author = {K. Padmanabhan}, title = {Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {2}, number = {4}, issn = {1045-9219}, year = {1991}, pages = {385-397}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.97896}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Parallel and Distributed Systems TI - Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors IS - 4 SN - 1045-9219 SP385 EP397 EPD - 385-397 A1 - K. Padmanabhan, PY - 1991 KW - Index Termscontrol tags; structural properties; traffic capacity; binary shuffle-exchange networks;multiprocessors; architecture; performance; connectivity; distributed tag-based controlalgorithm; source; destination; dynamic properties; stochastic environment; buffercapacity; multiprocessing systems; multiprocessor interconnection networks; parallelarchitectures; performance evaluation VL - 2 JA - IEEE Transactions on Parallel and Distributed Systems ER - | |||
The architecture and performance of binary shuffle-exchange networks of any size are investigated. It is established that a network with a shuffle-exchange stages whose number equals the least integer (or=log/sub 2/N) or a single recirculating stage can provide the connectivity between N inputs and N outputs using a distributed tag-based control algorithm. Control tags depend on both source and destination when N is not a power of two and can be computed in a simple manner. Several structural and dynamic properties of the network are established, contrasting the behavior of the power-of-two and composite sized systems. The performance of the network in a stochastic environment is investigated analytically. It is shown that the shuffle-exchange networks behave in much the same way with respect to traffic and buffer capacity regardless of whether the system size is a power of two or not.
[1] P.-Y. Chen, P.-C. Yew, and D. H. Lawrie, "Performance of packet switching in buffered single-stage shuffle-exchange networks," inProc. 3rd Int. Conf. Distributed Comput., May 1982, pp. 622-627.
[2] D. Z. Du and F. K. Hwang, "Generalized de Bruijn digraphs,"Networks, vol. 18, pp. 27-38, 1988.
[3] I. Gazit and M. Malek, "On the number of permutations performable by extra-stage multistage interconnection networks," inProc. 1987 Int. Conf. Parallel Processing, Aug. 1987, pp. 461-470.
[4] L. R. Goke and G. J. Lipovski, "Banyan networks for partitioning multiprocessor systems," inProc. 1st Annu. Symp. Comput. Architecture, Dec. 1973, pp. 21-28.
[5] S. W. Golomb, "Permutations by cutting and shuffling,"SIAM Rev., vol. 3, no. 4, pp. 293-297, Oct. 1961.
[6] M. Imase and M. Itoh, "Design to minimize diameter on building-block network,"IEEE Trans. Comput., vol. C-30, pp. 439-442, June 1981.
[7] L. Kleinrock,Queueing Systems, Vol. 1. New York: Wiley, 1975, ch. 5.
[8] C. P. Kruskal and M. Snir, "The performance of multistage interconnection networks for multiprocessors,"IEEE Trans. Comput., vol. C-32, pp. 1091-1098, Dec. 1983.
[9] C. P. Kruskal and M. Snir, "A unified theory of interconnection network structure,"Theoret. comput. Sci., vol. 48, pp. 75-94, 1986.
[10] T. Lang, "Interconnections between processors and memory modules using the shuffle-exchange network,"IEEE Trans. Comput., vol. C-25, pp. 496-503, May 1976.
[11] D. H. Lawrie and D. A. Padua, "Analysis of message switching with shuffle-exchange in multiprocessors," inProc. Workshop in Interconnection Networks for Parallel and Distributed Processing, Apr. 1980, pp. 116-123.
[12] D. H. Lawrie, "Memory-processor connection networks," Ph.D. dissertation, Univ. of Illinois at Urbana-Champaign, UMI #73-15783, Feb. 1973.
[13] D. H. Lawrie, "Access and alignment of data in an array processor,"IEEE Trans. Comput., vol. C-24, pp. 1145-1155, Dec. 1975.
[14] D. C. Opferman and N. T. Tsao-Wu, "On a class of rearrangeable switching networks, Part I: Control algorithm,"Bell Syst. Tech. J., vol. 50, no. 5, pp. 1579-1600, May-June 1971.
[15] K. Padmanabhan and D. H. Lawrie, "A class of redundant path multi-stage interconnection networks,"IEEE Trans. Comput., vol. C-32, pp. 1099-1108, Dec. 1983.
[16] J. H. Patel, "Performance of processor-memory interconnections for multiprocessors,"IEEE Trans. Comput., vol. C-30, pp. 771-780, Oct. 1981.
[17] M. C. Pease, "An adaptation of the fast Fourier transform for parallel processing,"J. ACM, vol. 15, pp. 252-264, 1968.
[18] H. S. Stone, "Parallel processing with the perfect shuffle,"IEEE Trans. Comput., vol. C-20, pp. 153-161, Feb. 1971.
[19] I. M. Vinogradov,Elements of Number Theory. New York: Dover, 1954, ch. III.
[20] P-C. Yew, D. A. Padua, and D. H. Lawrie, "Stochastic properties of a multiple-layer single-stage shuffle-exchange network in a message switching environment,"J. Digital Syst., vol. VI, no. 4, pp. 387-410, 1982.