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Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors
October 1991 (vol. 2 no. 4)
pp. 385-397

The architecture and performance of binary shuffle-exchange networks of any size are investigated. It is established that a network with a shuffle-exchange stages whose number equals the least integer (or=log/sub 2/N) or a single recirculating stage can provide the connectivity between N inputs and N outputs using a distributed tag-based control algorithm. Control tags depend on both source and destination when N is not a power of two and can be computed in a simple manner. Several structural and dynamic properties of the network are established, contrasting the behavior of the power-of-two and composite sized systems. The performance of the network in a stochastic environment is investigated analytically. It is shown that the shuffle-exchange networks behave in much the same way with respect to traffic and buffer capacity regardless of whether the system size is a power of two or not.

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Index Terms:
Index Termscontrol tags; structural properties; traffic capacity; binary shuffle-exchange networks;multiprocessors; architecture; performance; connectivity; distributed tag-based controlalgorithm; source; destination; dynamic properties; stochastic environment; buffercapacity; multiprocessing systems; multiprocessor interconnection networks; parallelarchitectures; performance evaluation
K. Padmanabhan, "Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors," IEEE Transactions on Parallel and Distributed Systems, vol. 2, no. 4, pp. 385-397, Oct. 1991, doi:10.1109/71.97896
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