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Orthogonal Graphs for the Construction of a Class of Interconnection Networks
January 1991 (vol. 2 no. 1)
pp. 3-19

A graph theoretical representation for a class of interconnection networks is suggested.The idea is based on a definition of orthogonal binary vectors and leads to a constructionrule for a class of orthogonal graphs. An orthogonal graph is first defined as a set of2/sup m/ nodes, which in turn are linked by 2/sup m-n/ edges for every link model definedin an integer set Q*. The degree and diameter of an orthogonal graph are determined interms of the parameters n, m, and the number of link modes defined in Q*. Routing inorthogonal graphs is shown to reduce to the node covering problem in bipartite graphs.The proposed theory is applied to describe a number of well-known interconnectionnetworks such as the binary m-cube and spanning-bus meshes. Multidimensional access (MDA) memories are also shown as examples of orthogonal shared memory multiprocessingsystems. Finally, orthogonal graphs are applied to the construction of multistageinterconnection networks. Connectivity and placement rules are given and shown to yielda number of well-known networks.

[1] H. M. Alnuweiri and V. K. P. Kumar, "A reduced mesh of trees organization for efficient solution to graph problems," inProc. 22nd Annu. Conf. Inform. Sci. Syst., Mar. 1988.
[2] H. M. Alnuweiri and V. K. P. Kumar, "Optimal image computations on reduced VLSI architectures,"IEEE Trans. Circuits Syst., Sept. 1989.
[3] K. E. Batcher, "The Flip network in STARAN," inProc. 1976 Int. Conf. Parallel Processing, 1976, pp. 65-71.
[4] K. E. Batcher, "The multidimensional access memory in STARAN,"IEEE Trans. Comput., vol. C-26, no. 2, pp. 172-177, Feb. 1977.
[5] K. E. Batcher, "Design of a massively parallel processor," IEEE Trans. Comput., Vol. C-29, no. 9, pp. 836-840, Sept. 1980.
[6] R. E. Buehreret al., "The ETH multiprocessor EMPRESS: A dynamically reconfigurable MIMD system,"IEEE Trans. Comput., vol. C-31, no. 11, pp. 1035-1044, Nov. 1982.
[7] L.N. Bhuyan and D. P. Agrawal, "Generalized hypercube and hyperbus structures for a computer network,"IEEE Trans. Comput., vol. C-33, no. 4, pp. 323-333, Apr. 1984.
[8] P. Chen, D. Lawrie, P. Yew, and D.A. Padua, "Interconnection networks using shuffles,"IEEE Comput. Mag., vol. 14, no. 12, pp. 55-64, Dec. 1981.
[9] G. Ezer, B. Hoyt, S. Sen, J.S. Sreekant, and I.D. Scherson, "A parallel processing architecture for image generation and processing." Tech. Rep. ECE 84-20. Dep. ECE, Univ. of California, Santa Barbara, Aug. 1984.
[10] T. Y. Feng, "Data manipulating functions in parallel processors and their implementations,"IEEE Trans. Comput., vol. C-23, no. 3, pp. 309-318, Mar. 1974.
[11] L. R. Goke and G. J. Lipovski, "Banyan networks for partitioning multiprocessor systems," inProc. 1st Annu. Symp. Comput. Architecture, Dec. 1973, pp. 21-28.
[12] A. Gottliebet al., "The NYU Ultracomputer-Designing an MIMD shared memory parallel computer,"IEEE Trans. Comput., vol. 32, no. 2, pp. 175-189, Feb. 1983.
[13] R. Grimaldi,Discrete and Combinatorial Mathematics-An Applied Introduction. Reading, MA: Addison-Wesley, 1985, pp. 141- 145.
[14] F. Harary,Graph Theory.Reading, MA: Addison-Wesley, 1969.
[15] K. Hwang and D. Kim, "Generalization of orthogonal multiprocessor for massively parallel computation," inProc. 2nd Frontiers MPC, Oct. 1988, pp. 391-398.
[16] K. Hwang, P. S. Tseng, and D. Kim, "An orthogonal multiprocessor for large-grain scientific computations,"IEEE Trans. Comput., vol. C-38, no. 1, pp. 47-61, Jan. 1989.
[17] IEEE Computer Magazine, Special Issue on Interconnection Networks, C-1. Wu, Ed., Dec. 1981.
[18] IEEE Computer Magazine, Special Issue on Interconnection Networks for Parallel and Distributed Computing, L. N. Bhuyan, Ed., June 1987.
[19] Z. Kohavi,Switching and Finite Automata Theory.New York: McGraw-Hill, 1978.
[20] T. Lang and H. S. Stone, "A shuffle-exchange network with simplified control,"IEEE Trans. Comput., vol. C-25, no. 1, pp. 55-65, Jan. 1976.
[21] T. Lang, "Interconnections between processors and memory modules using the shuffle-exchange network,"IEEE Trans. Comput., vol. C-25, no. 5, pp. 496-503, May 1976.
[22] D. H. Lawrie, "Access and alignment of data in an array processor,"IEEE Trans. Comput., vol. C-24, no. 12, pp. 1145-1155, Dec. 1975.
[23] D. H. Lawrie and D.A. Padua, "Analysis of message switching with shuffle-exchanges in multiprocessors," inProc. Workshop Interconnection Networks for Parallel and Distributed Processing, 1980, pp. 116-123.
[24] E. J. McCluskey, "Minimization of Boolean functions,"Bell Syst. Tech. J., vol. 35, no. 6, pp. 1417-1444, Nov. 1956.
[25] G. Memmi and Y. Raillard, "Some new results about the (d,k) graph problem,"IEEE Trans. Comput., vol. C-31, no. 8, pp. 784-791, Aug. 1982.
[26] D. Nath, S.N. Maheshwary, and P. C. Bhatt, "Efficient VLSI networks for parallel processing based on orthogonal trees,"IEEE Trans. Comput., vol. C-32, no. 6, pp. 569-581, June 1983.
[27] D. S. Parker, "Notes on shuffle/exchange-type networks,"IEEE Trans. Comput., vol. C-29, no. 3, pp. 213-222, Mar. 1980.
[28] M.C. Pease, "The indirect binaryn-cube microprocessor array,"IEEE Trans. Comput., vol. C-26, no. 5, pp. 458-473, May 1977.
[29] G. F. Pfisteret al., "The IBM research parallel processor prototype (RP3): Introduction and architecture," inProc. 1985 Int. Conf. Parallel Processing, 1985, pp. 764-771.
[30] D. K. Pradhan and K. L. Kodandapani, "A uniform representation of single- and multistage interconnection networks used in SIMD machines,"IEEE Trans. Comput., vol. C-29, no. 9, pp. 777-791, Sept. 1980.
[31] W. V. Quine, "The problem of simplifying truth functions,"Amer. Mathematics Monthly, vol. 59, no. 8, pp. 521-531, Oct. 1952.
[32] W. V. Quine, "A way to simplify truth functions,"Amer. Mathematics Monthly, vol. 62, no. 9, pp. 627-631, Nov. 1955.
[33] I. D. Scherson and Y. Ma, "Vector computations in an orthogonal memory access multiprocessing system," inProc. 8th Symp. Comput. Arithmetic, May 1987, pp. 28-37, Feb. 1989, pp. 238-249.
[34] I.D. Scherson, S. Sen, and Y. Ma, "Two nearly optimal sorting algorithms for mesh-connected processor arrays using shear-sort,"J. Parallel Distributed Comput., vol. 6, no. 1, pp. 151-165, Feb. 1989.
[35] I.D. Scherson and S. Sen, "Parallel sorting in two-dimensional VLSI models of computation,"IEEE Trans. Comput., vol. C-38, no. 2, pp. 238-249, Feb. 1989.
[36] I. D. Scherson and Y. Ma, "Analysis and applications of an orthogonal access multiprocessor,"J. Parallel Distributed Comput., vol. 7, pp. 232-255, 1989.
[37] I.D. Scherson, "A theory for the description and analysis of a class of interconnection networks," Princeton Univ. Tech. Rep. CE-S89-002.
[38] I.D. Scherson, "Definition and analysis of a class of spanning bus orthogonal multiprocessing systems," inProc. 1990 ACM Comput. Sci. Conf., Feb. 19-22, 1990, Washington, DC, pp. 194-200.
[39] I.D. Scherson, P.F. Corbett, and T. Lang, "An analytical characterization of generalized shuffle-exchange networks," inProc. INFOCOM'90, June 1990.
[40] C. L. Seitz, "The Cosmic Cube,"Commun. ACM, pp. 22-33, Jan. 1985.
[41] H. J. Siegel, "Analysis techniques for SIMD machine interconnection networks and the effects of processor address masks,"IEEE Trans. Comput., vol. C-26, no. 2, pp. 153-161, Feb. 1977.
[42] H. J. Siegel and S. D. Smith, "Study of multistage SIMD interconnection networks," inProc. 5th Annu. Symp. Comput. Architecture, Apr. 1978, pp. 223-229.
[43] H. J. Siegel, "The theory underlying the partitioning of permutations networks,"IEEE Trans. Comput., vol. C-29, no. 9, pp. 791-801, Sept. 1980.
[44] H. J. Siegel and R. J. McMillen, "The multistage cube: A versatile interconnection network,"IEEE Comput. Mag., vol. 14, no. 12, pp. 65-76, Dec. 1981.
[45] H. J. Siegel,Interconnectron Networks for Large-Scale Parallel Processing: Theory and Case Studies, second ed. New York: McGraw-Hill, 1990.
[46] H. S. Stone, "Parallel processing with the perfect shuffle,"IEEE Trans. Comput., vol. C-20, no. 2, pp. 153-161, Feb. 1971.
[47] Stone, H. S. 1987.High-Performance Computer Architecture. Reading, Mass., Addison-Wesley.
[48] P. S. Tseng, K. Hwang, and P. K. Kumar, "A VLSI-based multiprocessor architecture for implementing parallel algorithms," inProc. 13th Int. Conf. Parallel Processing, Aug. 1985.
[49] A. Tucker,Applied Combinatorics. New York: Wiley, 1980, pp. 109-112.
[50] L. D. Wittie, "Communication structures for large networks of microcomputers,"IEEE Trans. Comput., vol. C-30, no. 4, pp. 264-273, Apr. 1981.
[51] C. L. Wu and T. Y. Feng, "On a class of multistage interconnection networks,"IEEE Trans. Comput., vol. C-29, no. 8, pp. 694-702, Aug. 1980.
[52] C. L. Wu and T. Y. Feng, "The universality of the shuffle-exchange network,"IEEE Trans. Comput., vol. C-30, no. 5, pp. 324-332, May 1981.

Index Terms:
multidimensional access memories; connectivity; graph theoretical representation;interconnection networks; orthogonal binary vectors; link modes; node covering problem;bipartite graphs; binary m-cube; spanning-bus meshes; orthogonal shared memorymultiprocessing systems; placement; graph theory; multiprocessor interconnectionnetworks
Citation:
I.D. Scherson, "Orthogonal Graphs for the Construction of a Class of Interconnection Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 2, no. 1, pp. 3-19, Jan. 1991, doi:10.1109/71.80185
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