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On Mapping Systolic Algorithms onto the Hypercube
January 1990 (vol. 1 no. 1)
pp. 48-63

Consideration is given to the problem of mapping systolic array algorithms into efficient algorithms for a fixed-size hypercube architecture. The authors describe in detail several optimal implementations of algorithms given for one-way one- and two-dimensional systolic arrays. Since interprocessor communication is many times slower than local computation in parallel computers built to date, the problem of efficient communication is specifically addressed for these mappings. In order to validate the technique experimentally, five systolic algorithms were mapped in various ways onto a 64-node NCUBE/7 MIMD hypercube machine. The algorithms are for the following problems: the shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, matrix multiplication, and computing the Boolean transitive closure. Experimental evidence indicates that good performance is obtained for the mappings.

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Index Terms:
Index Termsparallel to parallel mappings; performance evaluation; time-space graph; one way linear systolic array; systolic algorithms; hypercube; systolic array algorithms; fixed-size hypercube architecture; two-dimensional systolic arrays; interprocessor communication; local computation; parallel computers; 64-node NCUBE/7 MIMD hypercube machine; shuffle scheduling problem; finite impulse response filtering; linear context-free language recognition; matrix multiplication; Boolean transitive closure; cellular arrays;computational complexity; parallel algorithms; parallel architectures
O.H. Ibarra, S.M. Sohn, "On Mapping Systolic Algorithms onto the Hypercube," IEEE Transactions on Parallel and Distributed Systems, vol. 1, no. 1, pp. 48-63, Jan. 1990, doi:10.1109/71.80124
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