|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown, "Overview of the SpiNNaker System Architecture," IEEE Transactions on Computers, vol. 99, no. 1, pp. , , 5555. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2012.142, author = {Steve B. Furber and David R. Lester and Luis A. Plana and Jim D. Garside and Eustace Painkras and Steve Temple and Andrew D. Brown}, title = {Overview of the SpiNNaker System Architecture}, journal ={IEEE Transactions on Computers}, volume = {99}, number = {1}, issn = {0018-9340}, year = {5555}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2012.142}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Overview of the SpiNNaker System Architecture IS - 1 SN - 0018-9340 SP EP EPD - A1 - Steve B. Furber, A1 - David R. Lester, A1 - Luis A. Plana, A1 - Jim D. Garside, A1 - Eustace Painkras, A1 - Steve Temple, A1 - Andrew D. Brown, PY - 5555 KW - Computer Systems Organization KW - Processor Architectures KW - Multiple Data Stream Architectures (Multiprocessors) KW - Parallel processors KW - Other Architecture Styles KW - Neurocomputers KW - Parallel Architectures KW - Real-time distributed KW - Interconnection architectures VL - 99 JA - IEEE Transactions on Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.142
SpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behaviour of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, communicating via packets carried by a custom interconnect fabric. The packets are small (40 or 72 bits), and their transmission is brokered entirely by hardware, giving the overall engine an extremely high bisection bandwidth of over 5 billion packets/s. Three of the principle axioms of parallel machine design -- memory coherence, synchronicity and determinism -- have been discarded in the design without, surprisingly, compromising the ability to perform meaningful computations. A further attribute of the system is the acknowledgement, from the initial design stages, that the sheer size of the implementation will make component failures an inevitable aspect of day-to-day operation, and fault detection and recovery mechanisms have been built into the system at many levels of abstraction. This paper describes the architecture of the machine and outlines the underlying design philosophy; software and applications are to be described in detail elsewhere, and only introduced in passing here as necessary to illuminate the description.
Index Terms:
Computer Systems Organization, Processor Architectures, Multiple Data Stream Architectures (Multiprocessors), Parallel processors, Other Architecture Styles, Neurocomputers, Parallel Architectures, Real-time distributed, Interconnection architectures
Citation:
Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown, "Overview of the SpiNNaker System Architecture," IEEE Transactions on Computers, 12 June 2012. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/TC.2012.142>
Usage of this product signifies your acceptance of the Terms of Use.

