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Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip
March 2014 (vol. 63 no. 3)
pp. 543-556
Hyungjun Kim, Texas A&M University, College Station
Boris Grot, EPFL, Lausanne
Paul V. Gratz, Texas A&M University, College Station
Daniel A. Jimenez, The University of Texas at San Antonio, San Antonio
As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and router-level switching activity. We specifically focus on memory subsystem traffic, as it comprises the bulk of NoC load in a CMP. By transmitting only the flits that contain words predicted useful using a novel spatial locality predictor, our scheme seeks to reduce network activity. We aim to further lower NoC energy through microarchitectural mechanisms that inhibit datapath switching activity for unused words in individual flits. Using simulation-based performance studies and detailed energy models based on synthesized router designs and different link wire types, we show that 1) the prediction mechanism achieves very high accuracy, with an average rate of false-unused prediction of just 2.5 percent; 2) the combined NoC energy savings enabled by the predictor and microarchitectural support is 36 percent, on average, and up to 57 percent in the best case; and 3) there is no system performance penalty as a result of this technique.
Index Terms:
Radiation detectors,Encoding,Wires,Energy consumption,Switches,Vectors,Memory management,interconnections,Power management,cache memory,spatial locality
Citation:
Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jimenez, "Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip," IEEE Transactions on Computers, vol. 63, no. 3, pp. 543-556, March 2014, doi:10.1109/TC.2012.238
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