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Issue No.03 - March (2014 vol.63)
pp: 527-528
Published by the IEEE Computer Society
Ran Ginosar , Technion, Israel Insitute of Technology, Israel
Karam S. Chatha , Qualcomm Research, San Diego, CA, USA
ABSTRACT
Network-on-Chip (NoC) has emerged as a key architecture component that determines the overall performance, power, and area (PPA) of a contemporary System-on-Chip (SoC) device. The PPA characteristics of NoC are influenced by a wide range of issues, including semi-conductor technology (process node and corner, 2D/3D integration), circuit technology (synchronous, asynchronous), SoC architecture and use-case (number of IP blocks, general purpose or domain specific workload, frequency requirements, voltage, and clock domains), network topology (homogeneous, heterogeneous), routing strategy (deterministic, adaptive), router architecture and features (arity, virtual channels, Quality-of-Service, or QoS), and test architecture. Consequently, research in NoC design covers a wide gamut of topics. This special issue presents the latest advancements in NoC design and optimization.
Introduction
Network-on-Chip or NoC has emerged as a key architecture component that determines the overall performance, power, and area (PPA) of a contemporary System-on-Chip (SoC) device. The PPA characteristics of NoC are influenced by a wide range of issues, including semi-conductor technology (process node and corner, 2D/3D integration), circuit technology (synchronous, asynchronous), SoC architecture and use-case (number of IP blocks, general purpose or domain specific workload, frequency requirements, voltage, and clock domains), network topology (homogeneous, heterogeneous), routing strategy (deterministic, adaptive), router architecture and features (arity, virtual channels, Quality-of-Service), and test architecture. Consequently, research in NoC design covers a wide gamut of topics. This special issue presents the latest advancements in NoC design and optimization.
The special issue begins with four papers focused on NoC routing strategies and topology adaptation. The paper titled “Holistic Routing Algorithm Design to Support Workload Consolidation in NoCS” presents an adaptive routing strategy that addresses interference due to workload consolidation encountered in many-core systems. The following paper, “Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip,” aims at reducing memory-subsystem network energy consumption by predicting and transmitting only useful words. The paper titled “Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead” proposes an approach for reducing the hardware overhead associated with routing in custom irregular NoC. The paper titled “Exploiting Emergence in On-Chip Interconnects” presents a technique for reducing NoC latency via runtime topology reconfiguration.
The next three papers focus on supporting Quality-of-Service (QoS) requirements in NoC. The paper titled “dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up” discusses an NoC router design that provides guaranteed throughput services with multicast support. The next paper, “Differentiated Communication Services for NoC-Based MPSoCs,” proposes an API that enables the application programmer to exploit the QoS mechanism implemented in the NoC. The paper titled “Design of a NoC Interface Macrocell with Hardware Support of Advanced Networking Functionalities” presents an NoC interface that supports several functionalities, including error control, power management, ordering, security, and QoS.
The following two papers address topics in NoC router design. The paper titled “MoDe-X: Microarchitecture of a Layout-Aware Modular Decoupled Crossbar for On-Chip Interconnects” presents a layout aware crossbar design with lower power consumption and area requirements in comparison to previous work. The following paper, “High-Throughput Compact Delay-Insensitive Asynchronous NoC Router,” presents an asynchronous router design based on level-encoded dual rail encoding.
The next three papers discuss simulation and automated tools for NoC design. The paper titled “PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks” presents a trace-based NoC simulation framework that incorporates dependency information between packets. The paper “DART: A Programmable Architecture for NoC Simulation on FPGAs” presents a parameterizable FPGA-based simulator that is able to simulate different NoC topologies. The next paper, “Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip,” presents a tool infrastructure (models for power grid and NoC performance/power consumption) for determining NoC $V_{DD}$ drops.
The following two papers address topics on NoC test and validation. The paper titled “Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs” addresses the problem of assigning automated test equipment pins (tester channels) to NoC access point with an objective of reducing the overall test time. The next paper, “At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs,” presents a scalable test approach for detecting stuck-at and delay faults in NoC.
The next three papers address topics in 3D and wireless NoC technologies. The paper titled “Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing” explores approaches for routing unicast and multicast traffic in 3D mesh-based NoC. The paper “High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET-Based Adaptive Monitoring Platform” presents a hybrid NoC-bus based interconnect for 3D ICs. The paper titled “3-D NoC with Inductive-Coupling Links for Building-Block SiPs” presents a wireless approach for inter-die communication within a System-in-Package (SiP).
The final two papers in the special issue address photonic NoC architectures. The paper titled “Design of a Bufferless Photonic Clos Network-on-Chip Architecture” presents a photonic Clos NoC architecture that addresses output contention, path allocation, and laser-power budget challenges. The paper “All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip” presents an all optical NoC architecture with a novel topology and routing algorithm.
The papers comprising this special issue on NoC were first presented in shorter forms at NOCS 2011, the Fifth ACM/IEEE International Symposium on Networks-on-Chip, held in 2011 in Pittsburgh, Pennsylvania. An open-to-all Call for Papers for this special issue was published in 2011 and many papers were submitted. A long anonymous peer review process, involving referees from the original Technical Program Committee of NOCS 2011 and other reviewers, was carried out according to the rules and practices of the IEEE Transactions on Computers. While some papers were accepted with only minor revisions, others underwent major revisions and some papers had to be resubmitted as new papers, finally resulting in the 19 papers published in this special issue on NoC. We are extremely grateful to the numerous referees for many months of careful review, to the Transactions team for nonstop support over a very long period, and especially to the authors for submitting their papers, for meticulously following all guidelines and recommendations given by the reviewers, and for their patience. Thanks to all these efforts, the special issue now constitutes a significant contribution to the research and practice of Network-on-Chip.
Ran Ginosar
Karama S. Chatha
Guest Editors

    R. Ginosar is with the Technion Israel Insitute of Technology, Israel.

    E-mail: ran@ee.technion.ac.il.

    K.S. Chatha is with Qualcomm Research, San Diego, CA.

    E-mail: Karamvir.Chatha@asu.edu.

For information on obtaining reprints of this article, please send e-mail to: tc@computer.org.



Ran Ginosar received the BSc degree from the Technion Israel Institute of Technology in 1978 ( scl) and the PhD degree from Princeton University, Princeton, New Jersey, in 1982, both in electrical and computer engineering. He worked at AT&T Bell Laboratories in 1982-1983, and joined the Technion faculty in 1983. He was a visiting associate professor with the University of Utah in 1989-1990, and a visiting faculty member with Intel Research Labs in 1997-1999. He is an associate professor with the Departments of Electrical Engineering and Computer Science and serves as head of the VLSI Systems Research Center at the Technion. His research interests include VLSI architecture, manycore computers, asynchronous logic and synchronization, networks on chip, and biologic implant chips. He has co-founded several companies in various areas of VLSI systems. He is a senior member of the IEEE.



Karam S. Chatha received the BE degree (with honors) in computer technology from Bombay University, Mumbai, India, in 1993, and the MS and PhD degrees in computer science and engineering from the University of Cincinnati, Cincinnati, Ohio, in 1997 and 2001, respectively. He is currently a principal engineer at Qualcomm Research, San Diego, California. His research interests include embedded systems, with emphasis on system-level design of hardware and software. Specifically, he has focused on network-on-chip design, parallel programming and compilation on embedded multi-core processors, low power and thermal aware design, multiprocessor system-on-chip design, hardware-software co-design, and reconfigurable and adaptive computing. Dr. Chatha served as the General Chair for NOCS '13, Vice General Chair for ESWEEK '13, Program Chair for NOCS '11, and on the technical program committees of several international conferences (DAC, DATE, ICCAD, CODES-ISSS). He was a recipient of the US National Science Foundation CAREER Award in 2006. His publications were recognized with the Best Paper Award at the International Conference on Computer Aided Design in 2007 and the International Workshop on Field Programmable Logic in 1999. He is a member of the IEEE and the ACM.
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