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Issue No.11 - Nov. (2013 vol.62)
pp: 2238-2251
Jonghun Yoo , Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
Jaesoo Lee , Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
Seongsoo Hong , Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
A flash translation layer (FTL) provides file systems with transparent access to NAND flash memory. Although many applications running on it require real-time guarantees, it is difficult to provide tight worst case execution time (WCET) bounds with conventional static WCET analysis since an FTL exhibits a large variance in execution time depending on its runtime state. Parametric WCET analysis could be an effective alternative but it is also challenging to formulate a parametric WCET function for an FTL program because traditional FTL architecture does not properly model the runtime availability of flash resources in its code structure. To overcome such a limitation, we propose Petri net-based FTL architecture where a Petri net explicitly specifies dependencies between FTL operations and the runtime resource availability. It comes with an FTL operation sequencer that derives at runtime the shortest sequence of FTL operations for servicing an incoming FTL request under the current resource availability. The sequencer computes the WCET of the request by merely summing the WCETs of only those FTL operations in the sequence. Our experimental results show the effectiveness of our FTL architecture. It allowed for tight WCET estimation that yielded WCETs shorter by a factor of 54 than statically analyzed ones.
software architecture, flash memories, logic gates, Petri nets, program diagnostics,runtime resource availability, Petri net-based FTL architecture, parametric WCET estimation, FTL operation sequence derivation, flash translation layer, file systems, transparent access, NAND flash memory, worst case execution time, static WCET analysis, execution time, parametric WCET analysis, parametric WCET function, FTL program, flash resources, code structure,Petri nets, Real-time systmes, Software architecture,performance modeling and prediction, Real-time and embedded systems, software architectures
Jonghun Yoo, Jaesoo Lee, Seongsoo Hong, "Petri Net-Based FTL Architecture for Parametric WCET Estimation via FTL Operation Sequence Derivation", IEEE Transactions on Computers, vol.62, no. 11, pp. 2238-2251, Nov. 2013, doi:10.1109/TC.2012.114
[1] J. Yoon et al., "Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture," Computer Architecture Letters, vol. 7, pp. 17-20, 2007.
[2] Y.J. Seong et al., "Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture," IEEE Trans. Computers, vol. 59, no. 7, pp. 905-921, July 2010.
[3] T.S. Chung et al., "A Survey of Flash Translation Layer," J. Systems Architecture, vol. 55, pp. 332-343, May/June 2009.
[4] E. Gal and S. Toledo, "Algorithms and Data Structures for Flash Memories," ACM Computing Surveys, vol. 37, pp. 138-163, June 2005.
[5] R. Wilhelm et al., "The Worst-Case Execution-Time Problem - Overview of Methods and Survey of Tools," ACM Trans. Embedded Computing Systems, vol. 7, no. 3,article no. 36, Apr. 2008.
[6] P. Puschner and A. Burns, "A Review of Worst-Case Execution-Time Analysis," Real-Time Systems, vol. 18, pp. 115-128, May 2000.
[7] S. Byhlin, A. Ermedahl, J. Gustafsson, and B. Lisper, "Applying Static WCET Analysis to Automotive Communication Software," Proc. 17th Euromicro Conf. Real-Time Systems (ECRTS '05), pp. 249-258, 2005.
[8] G. Bernat and A. Burns, "An Approach to Symbolic Worst-Case Execution Time Analysis," Proc. Workshop Real-Time Programming, 2000.
[9] E. Vivancos, C. Healy, F. Mueller, and D. Whalley, "Parametric Timing Analysis," ACM SIGPLAN Notices, vol. 36, pp. 88-93, Aug. 2001.
[10] S. Mohan et al., "Parametric Timing Analysis and Its Application to Dynamic Voltage Scaling," ACM Trans. Embedded Computing Systems, vol. 10, no. 2,article no. 25, Dec. 2010.
[11] B. Lisper, "Fully Automatic, Parametric Worst-Case Execution Time Analysis," Proc. Workshop Worst-Case Execution Time Analysis (WCET '03), pp. 99-102, 2003.
[12] S. Altmeyer, C. Humbert, B. Lisper, and R. Wilhelm, "Parametric Timing Analysis for Complex Architectures," Proc. IEEE Embedded and Real-Time Computing Systems and Applications (RTCSA '08), pp. 367-376, 2008.
[13] S. Bygde and B. Lisper, "Towards an Automatic Parametric WCET Analysis," Proc. Wrokshop Worst-Case Execution Time Analysis (WCET '08), 2008.
[14] C. Park et al., "A Reconfigurable FTL (Flash Translation Layer) Architecture for NAND Flash-Based Applications," ACM Trans. Embedded Computing Systems, vol. 7, no. 4,article no. 38, July 2008.
[15] D. Jung, J.U. Kang, H. Jo, J.S. Kim, and J. Lee, "Superblock FTL: A Superblock-Based Flash Translation Layer with a Hybrid Address Translation Scheme," ACM Trans. Embedded Computing Systems, vol. 9, no. 4,article no. 40, Mar. 2010.
[16] S.W. Lee et al., "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation," ACM Trans. Embedded Computing Systems, vol. 6, no. 3,article no. 18, July 2007.
[17] L. Chang, T. Kuo, and S. Lo, "Real-Time Garbage Collection for Flash-Memory Storage Systems of Real-Time Embedded Systems," ACM Trans. Embedded Computing Systems, vol. 3, pp. 837-863, 2004.
[18] J. Kim, J.M. Kim, S.H. Noh, S.L. Min, and Y. Cho, "Space-Efficient Flash Translation Layer for Compactflash Systems," IEEE Trans. Consumer Electronics, vol. 48, no. 2, pp. 366-375, May 2002.
[19] H. Kwon, E. Kim, J. Choi, D. Lee, and S.H. Noh, "Janus-FTL: Finding the Optimal Point on the Spectrum Between Page and Block Mapping Schemes," Proc. ACM Int'l Conf. Embedded Software (EMSOFT '10), pp. 169-178, 2010.
[20] T. Murata, "Petri Nets - Properties, Analysis and Applications," Proc. IEEE, vol. 77, no. 4, pp. 541-580, Apr. 1989.
[21] R. Lipton, The Reachability Problem Requires Exponential Space. Computer Science Dept., Yale Univ., 1976.
[22] G. Chiola, C. Dutheillet, G. Franceschinis, and S. Haddad, "Stochastic Well-Formed Colored Nets and Symmetrical Modeling Applications," IEEE Trans. Computers, vol. 42, no. 11, pp. 1343-1360, Nov. 1993.
[23] J. Ezpeleta, J.M. Colom, and J. Martinez, "A Petri-Net Based Deadlock Prevention Policy for Flexible Manufacturing Systems," IEEE Trans. Robotics and Automation, vol. 11, no. 2, pp. 173-184, Apr. 1995.
[24] M.D. Jeng and F. Dicesare, "Synthesis Using Resource Control Nets for Modeling Shared-Resource Systems," IEEE Trans. Robotics and Automation, vol. 11, no. 2, pp. 317-327, June 1995.
[25] W.M.P. Van der Aalst, "The Application of Petri Nets to Workflow Management," J. Circuits Systems and Computers, vol. 8, pp. 21-66, Feb. 1998.
[26] G. Berthelot, "Transformations and Decompositions of Nets," Proc. Advanced Course on Petri Nets: Central Models and Their Properties, Advances in Petri Nets Conf., vol. 254, pp. 359-376, 1987.
[27] J.M. Colom and M. Silva, "Improving the Linearly Based Characterization of P/T Nets," Proc. 10th Int'l Confe. Applications and Theory of Petri Nets: Advances in Petri Nets, vol. 483, pp. 113-145, 1991.
[28] P. Godefroid, "Using Partial Orders to Improve Automatic Verification Methods," Proc. Second Int'l Workshop Computer Aided Verification, vol. 531, pp. 176-185, 1991.
[29] K. McMillan, "Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits," Proc. Fourth Int'l Workshop Computer Aided Verification, vol. 663, pp. 164-177, 1993.
[30] A. Valmari, "Stubborn Sets for Reduced State-Space Generation," Proc. 10th Int'l Conf. Applications and Theory of Petri Nets: Advances in Petri Nets, vol. 483, pp. 491-515, 1991.
[31] F. Feldbrugge, "Petri Net Tool Overview 1992," Advances in Petri Nets, pp. 169-209, Springer, 1993.
[32] A.V. Ratzer et al., "CPN Tools for Editing, Simulating, and Analysing Coloured Petri Nets," Proc. Applications and Theory of Petri Nets, vol. 2679, pp. 450-462, 2003.
[33] R.G. Willson and B.H. Krogh, "Petri Net Tools for the Specification and Analysis of Discrete Controllers," IEEE Trans. Software Eng., vol. 16, no. 1, pp. 39-50, Jan. 1990.
[34] K.H. Mortensen, "Automatic Code Generation Method Based on Coloured Petri net Models Applied on an Access Control System," Proc. Application and Theory of Petri Nets Conf., vol. 1825, pp. 367-386, 2000.
[35] Samsumg, (2007, NAND Flash, SLC-Large Block, K9F8G08U0M, K9F8G08U0M&xFmly_id=157#component02 , 2013.
[36] W. Norcutt Iozone File System Benchmark,: http:/www., 2006.
[37] D. Sandell, A. Ermedahl, J. Gustafsson, and B. Lisper, "Static Timing Analysis of Real-Time Operating System Code," Proc. Int'l Symp. Leveraging Applications of Formal Methods (ISoLA '04), 2004.
[38] J. Coffman, C. Healy, F. Mueller, and D. Whalley, "Generalizing Parametric Timing Analysis," Proc. ACM SIGPLAN/SIGBED Conf. Languages, Compilers, and Tools for Embedded Systems (LCTES '07), pp. 152-154, 2007.
[39] S. Mohan et al., "ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling," Proc. Real-Time Systems Symp. (RTSS '05), pp. 10-242, 2005.
[40] F. Mueller, "Timing Analysis: In Search of Multiple Paradigms," Proc. Int'l Parallel and Distributed Processing Symp. (IPDPS '04), p. 126, 2004.
[41] F. Burns, A. Koelmans, and A. Yakovlev, "WCET Analysis of Superscalar Processors using Simulation with Coloured Petri Nets," Real-Time Systems, vol. 18, pp. 275-288, May 2000.
[42] F. Stappert, "Petri Net Level WCET Analysis," Proc. Workshop Worst-Case Execution Time Analysis (WCET '04), pp. 63-66, 2004.
[43] F. Rammig and C. Rust, "Modeling of Dynamically Modifiable Embedded Real-Time Systems," Proc. IEEE Int'l Workshop Object-Oriented Real-Time Dependable Systems, pp. 28-34, 2003.
[44] F. Stappert and C. Rust, "Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems," Proc. Int'l Conf. Embedded Systems and Applications, pp. 176-182, 2003.
[45] M. Heiner and L. Popova-Zeugmann, "Worst Case Analysis of Concurrent Systems with Duration Interval Petri Nets," Professoren des Inst. of für Informatik, 1997.
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