Subscribe

Issue No.11 - Nov. (2013 vol.62)

pp: 2196-2209

Ioannis Kouretas , University of Patras, Patras

Charalambos Basetas , University of Patras, Patras

Vassilis Paliouras , University of Patras, Patras

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.111

ABSTRACT

This paper presents techniques for low-power addition/subtraction in the logarithmic number system (LNS) and quantifies their impact on digital filter VLSI implementation. The impact of partitioning the look-up tables required for LNS addition/subtraction on complexity, performance, and power dissipation of the corresponding circuits is quantified. Two design parameters are exploited to minimize complexity, namely the LNS base and the organization of the LNS word. A roundoff noise model is used to demonstrate the impact of base and word length on the signal-to-noise ratio of the output of finite impulse response (FIR) filters. In addition, techniques for the low-power implementation of an LNS multiply accumulate (MAC) units are investigated. Furthermore, it is shown that the proposed techniques can be extended to cotransformation-based circuits that employ interpolators. The results are demonstrated by evaluating the power dissipation, complexity and performance of several FIR filter configurations comprising one, two or four MAC units. Simulations of placed and routed VLSI LNS-based digital filters using a 90-nm 1.0 V CMOS standard-cell library reveal that significant power dissipation savings are possible by using optimized LNS circuits at no performance penalty, when compared to linear fixed-point two's-complement equivalents.

INDEX TERMS

Table lookup, Complexity theory, Power dissipation, Organizations, Adders, Finite impulse response filter,FIR, Logarithmic number system, computer arithmetic, digital filter

CITATION

Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras, "Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters",

*IEEE Transactions on Computers*, vol.62, no. 11, pp. 2196-2209, Nov. 2013, doi:10.1109/TC.2012.111REFERENCES

- [1] T. Stouraitis and V. Paliouras, "Considering the Alternatives in Low-Power Design,"
IEEE Circuits and Devices, vol. 17, no. 4, pp. 23-29, July 2001.- [2] P.E. Landman and J.M. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method,"
IEEE Trans. Very Large Scale Integration Systems, vol. 3, no. 2, pp. 173-187, June 1995.- [3] K.-H. Chen and T.-D. Chiueh, "A Low-Power Digit-Based Reconfigurable FIR Filter,"
IEEE Trans. Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp. 617-621, Aug. 2006.- [4] E. Swartzlander and A. Alexopoulos, "The Sign/Logarithm Number System,"
IEEE Trans. Computers, vol. 24, no. 12, pp. 1238-1242, Dec. 1975.- [5] M.G. Arnold, T.A. Bailey, J.R. Cowles, and M.D. Winkel, "Applying Features of the IEEE 754 to Sign/Logarithm Arithmetic,"
IEEE Trans. Computers, vol. 41, pp. 1040-1050, Aug. 1992.- [6] J. Coleman, C. Softley, J. Kadlec, R. Matousek, M. Tichy, Z. Pohl, A. Hermanek, and N. Benschop, "The European Logarithmic Microprocesor,"
IEEE Trans. Computers, vol. 57, no. 4, pp. 532-546, Apr. 2008.- [7] V. Mahalingam and N. Ranganathan, "Improving Accuracy in Mitchell's Logarithmic Multiplication using Operand Decomposition,"
IEEE Trans. Computers, vol. 55, no. 12, pp. 1523-1535, Dec. 2006.- [8] K. Johansson, O. Gustafsson, and L. Wanhammar, "Implementation of Elementary Functions for Logarithmic Number Systems,"
IET Computers and Digital Techniques, vol. 2, no. 4, pp. 295-304, http://link.aip.org/link/?CDT/2/2951, 2008.- [9] M.G. Arnold, T.A. Bailey, J.R. Cowles, and M.D. Winkel, "Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems,"
IEEE Trans. Computers, vol. 47, no. 7, pp. 777-786, July 1998.- [10] V.S. Dimitrov, G.A. Jullien, and W.C. Miller, "Theory and Applications of the Double-Base Number System,"
IEEE Trans. Computers, vol. 48, no. 10, pp. 1098-1106, Oct. 1999.- [11] R. Muscedere, V. Dimitrov, G. Jullien, and W. Miller, "Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion using Range-Addressable Look-Up Tables,"
IEEE Trans. Computers, vol. 54, no. 3, pp. 257-271, Mar. 2005.- [12] R.C. Ismail and J.N. Coleman, "ROM-less LNS,"
Proc. IEEE Symp. Computer Arithmetic, pp. 43-51, 2011.- [13] H. Fu, O. Mencer, and W. Luk, "FPGA Designs with Optimized Logarithmic Arithmetic,"
IEEE Trans. Computers, vol. 59, no. 7, pp. 1000-1006, July 2010.- [14] M. Arnold and S. Collange, "A Real/Complex Logarithmic Number System ALU,"
IEEE Trans. Computers, vol. 60, no. 2, pp. 202-213, Feb. 2011.- [15] R.E. MorleyJr., G.L. Engel, T.J. Sullivan, and S.M. Natarajan, "VLSI Based Design of a Battery-Operated Digital Hearing Aid,"
Proc. IEEE Int'l Conf. Acoustics, Speech and Signal Processing, pp. 2512-2515, 1988.- [16] J.R. Sacha and M.J. Irwin, "Number Representation for Reducing Switched Capacitance in Subband Coding,"
Proc. IEEE Int'l Conf. Acoustics, Speech and Signal Processing (ICASSP), pp. 3125-3128, 1998.- [17] M.G. Arnold, "Reduced Power Consumption for MPEG Decoding with LNS,"
Proc. IEEE Int'l Conf. Application-Specific Systems, Architectures and Processors, (ASAP 02), pp. 65-67, 2002.- [18] B. Kang, N. Vijaykrishnan, M.J. Irwin, and T. Theocharides, "Power-Efficient Implementation of Turbo Decoder in SDR System,"
Proc. IEEE Int'l SOC Conf., pp. 119-122, 2004.- [19] P. Robertson, E. Villebrun, and P. Hoeher, "A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the log Domain,"
Proc. IEEE Int'l Conf. Comm., pp. 1009-1013, June 1995.- [20] H. Wang, H. Yang, and D. Yang, "Improved Log-MAP Decoding Algorithm for Turbo-Like Codes,"
IEEE Comm. Letters, vol. 10, no. 3, pp. 186-188, Mar. 2006.- [21] R. Peng and R.-R. Chen, "Application of Nonbinary LDPC Codes for Communication over Fading Channels using Higher Order Modulations,"
IEEE Global Telecomm. Conf. (GLOBECOM '06), pp. 1-5, Dec. 2006.- [22] V. Paliouras and T. Stouraitis, "Low-Power Properties of the Logarithmic Number System,"
Proc. 15th Symp. Computer Arithmetic (ARITH), pp. 229-236, June 2001.- [23] V. Paliouras and T. Stouraitis, "Logarithmic Number System for Low-Power Arithmetic,"
Proc. Int'l Workshop - Power and Timing Modeling, Optimization and Simulation, (PATMOS '00), pp. 285-294, 2000.- [24] C. Basetas, I. Kouretas, and V. Paliouras, "Low-Power Digital Filtering Based on the Logarithmic Number System,"
Proc. 17th Workshop Power and Timing Modeling, Optimization and Simulation, LNCS4644, pp. 546-555, 2007.- [25] I. Kouretas, C. Basetas, and V. Paliouras, "Low-Power Logarithmic Number System Addition/Subtraction and their Impact on Digital Filters,"
Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '08), pp. 692-695, 2008.- [26] S. Galal and M. Horowitz, "Energy-Efficient Floating-Point Unit Design,"
IEEE Trans. Computers, vol. 60, no. 7, pp. 913-922, July 2011.- [27] H. Henkel, "Improved Addition for the Logarithmic Number System,"
IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 37, no. 2, pp. 301-303, Feb. 1989.- [28] D. Lewis and L. Yu, "Algorithm Design for a 30 Bit Integrated Logarithmic Processor,"
Proc. Ninth Symp. Computer Arithmetic, pp. 192-199, 1989.- [29] J. Coleman, "Simplification of Table Structure in Logarithmic Arithmetic,"
Electronics Letters, vol. 31, no. 22, pp. 1905-1906, Oct. 1995.- [30] V. Paliouras and T. Stouraitis, "A Novel Algorithm for Accurate Logarithmic Number System Subtraction,"
Proc. IEEE Symp. Circuits and Systems (ISCAS '96), vol. 4, pp. 268-271, May 1996.- [31] I. Orginos, V. Paliouras, and T. Stouraitis, "A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction using Polynomial Approximation,"
Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '95), pp. III.1992-III.1995, 1995.- [32] S. Collange, J. Detrey, and F. de Dinechin, "Floating-Point or LNS: Choosing the Right Arithmetic on an Application Basis,"
Proc. Ninth Euromicro Conf. Digital System Design (DSD '06), pp. 197-203, 2006.- [33] P.D. Vouzis, S. Collange, and M.G. Arnold, "Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction,"
Proc. 10th Euromicro Conf. Digital System Design (DSD '07), pp. 85-93, 2007.- [34] J.-M. Muller,
Elementary Functions - Algorithms and Implementation. Hamilton Printing, 1997.- [35] S. Paul, N. Jayakumar, and S. Khatri, "A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations,"
IEEE Trans. Very Large Scale Integration Systems, vol. 17, no. 2, pp. 269-277, Feb. 2009.- [36] J. Kurokawa, T. Payne, and S. Lee, "Error Analysis of Recursive Digital Filters Implemented with Logarithmic Number Systems,"
IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 28, no. 6, pp. 706-715, Dec. 1980.- [37] F. Taylor, R. Gill, J. Joseph, and J. Radke, "A 20 bit Logarithmic Number System Processor,"
IEEE Trans. Computers, vol. 37, no. 5, pp. 190-199, Feb. 1988.- [38] http:/www.synopsys.com, 2013.
- [39] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi,
Low Power Methodology Manual: For System-on-Chip Design. Springer Publishing Company, Inc., 2007.- [40] C.-H. Chang, J. Chen, and A. Vinod, "Information Theoretic Approach to Complexity Reduction of FIR Filter Design,"
IEEE Trans. Circuits and Systems - Part I, vol. 55, no. 8, pp. 2310-2321, Sept. 2008.- [41] M. Aktan, A. Yurdakul, and G. Dundar, "An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters,"
IEEE Trans. Circuits and Systems - Part I, vol. 55, no. 6, pp. 1536-1545, July 2008.- [42] D. Chandra, "Error Analysis of FIR Filters Implemented Using Logarithmic Arithmetic,"
IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 6, pp. 744-747, June 1998.- [43] A. Papoulis,
Probability, Random Variables, and Stochastic Processes, third ed. McGraw-Hill, 1991.- [44] T.K. Callaway and E.E. SwartzlanderJr., "Power-Delay Characteristics of CMOS Multipliers,"
Proc. 13th Symp. Computer Arithmetic (ARITH), pp. 26-32, July 1997. |