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Issue No.10 - Oct. (2013 vol.62)
pp: 1959-1971
Zhemin Zhang , Stony Brook University, Stony Brook
Zhiyang Guo , Stony Brook University, Stony Brook
Yuanyuan Yang , Stony Brook University, Stony Brook
With the development of multiprocessor system on chips (MPSoCs), it is expected that hundreds of computing cores will be operating on a single chip in the near future. This will require high-performance on-chip networks with very low latency to provide a communication substrate for the increasing number of cores. In this paper, we consider Gaussian on-chip networks that are of significant topological advantages over traditional mesh and torus networks in terms of diameter and average hop distance. Many applications on MPSoCs need global data movement and global control to exchange data and synchronize the execution among cores, which require all-to-all broadcast communication. In this paper, we propose an all-to-all broadcast algorithm suitable for on-chip implementation on the Gaussian network topology. The algorithm utilizes controlled message flooding based on a broadcast pattern, which can be described in a formal, generic way for each node in terms of a few simple operations and can be easily built into router hardware. Furthermore, the generic broadcast pattern also ensures a balanced traffic load in all dimensions in the network so that minimum total latency for all-to-all broadcast can be achieved. The algorithm overlaps message switching time with transmission time in a pipelined fashion to further reduce the total communication latency of all-to-all broadcast. Comparison results demonstrate the topological merits of Gaussian networks and ultralow latency of the proposed all-to-all broadcast algorithm.
System-on-a-chip, Network topology, Algorithm design and analysis, Delay, Topology, Clocks, Routing, Gaussian network, Network on chips, all-to-all broadcasting, hardware-based, pipeline, routing, multiprocessor system on chip
Zhemin Zhang, Zhiyang Guo, Yuanyuan Yang, "Efficient All-to-All Broadcast in Gaussian On-Chip Networks", IEEE Transactions on Computers, vol.62, no. 10, pp. 1959-1971, Oct. 2013, doi:10.1109/TC.2012.126
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