This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions
Aug. 2013 (vol. 62 no. 8)
pp. 1597-1606
M. Soltiz, Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
D. Kudithipudi, Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
C. Merkel, Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
G. S. Rose, Trusted Syst. Branch, Air Force Res. Lab./RITA, Rome, NY, USA
R. E. Pino, ICF Int., Fairfax, VA, USA
Neural logic blocks (NLBs) enable the realization of biologically inspired reconfigurable hardware. Networks of NLBs can be trained to perform complex computations such as multilevel Boolean logic and optical character recognition (OCR) in an area- and energy-efficient manner. Recently, several groups have proposed perceptron-based NLB designs with thin-film memristor synapses. These designs are implemented using a static threshold activation function, limiting the set of learnable functions to be linearly separable. In this work, we propose two NLB designs-robust adaptive NLB (RANLB) and multithreshold NLB (MTNLB)-which overcome this limitation by allowing the effective activation function to be adapted during the training process. Consequently, both designs enable any logic function to be implemented in a single-layer NLB network. The proposed NLBs are designed, simulated, and trained to implement ISCAS-85 benchmark circuits, as well as OCR. The MTNLB achieves 90 percent improvement in the energy delay product (EDP) over lookup table (LUT)-based implementations of the ISCAS-85 benchmarks and up to a 99 percent improvement over a previous NLB implementation. As a compromise, the RANLB provides a smaller EDP improvement, but has an average training time of only ≈ 4 cycles for 4-input logic functions, compared to the MTNLBs ≈ 8-cycle average training time.
Index Terms:
transfer functions,benchmark testing,biocomputing,logic design,memristors,optical character recognition,perceptrons,power aware computing,reconfigurable architectures,table lookup,4-input logic functions,memristor-based neural logic blocks,nonlinearly separable functions,biologically inspired reconfigurable hardware realization,perceptron-based NLB designs,thin-film memristor synapses,static threshold activation function,robust adaptive NLB,RANLB,multithreshold NLB,MTNLB,training process,logic function,single-layer NLB network,ISCAS-85 benchmark circuits,OCR,optical character recognition,multilevel Boolean logic,energy delay product,EDP,lookup table,LUT-based implementations,ISCAS-85 benchmarks,Self-organizing networks,Neural networks,Biological system modeling,neural networks,Neuromorphic,stochastic gradient descent,memristors,OCR,reconfigurable logic
Citation:
M. Soltiz, D. Kudithipudi, C. Merkel, G. S. Rose, R. E. Pino, "Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions," IEEE Transactions on Computers, vol. 62, no. 8, pp. 1597-1606, Aug. 2013, doi:10.1109/TC.2013.75
Usage of this product signifies your acceptance of the Terms of Use.