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Issue No.08  Aug. (2013 vol.62)
pp: 15971606
M. Soltiz , Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
D. Kudithipudi , Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
C. Merkel , Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
G. S. Rose , Trusted Syst. Branch, Air Force Res. Lab./RITA, Rome, NY, USA
R. E. Pino , ICF Int., Fairfax, VA, USA
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2013.75
ABSTRACT
Neural logic blocks (NLBs) enable the realization of biologically inspired reconfigurable hardware. Networks of NLBs can be trained to perform complex computations such as multilevel Boolean logic and optical character recognition (OCR) in an area and energyefficient manner. Recently, several groups have proposed perceptronbased NLB designs with thinfilm memristor synapses. These designs are implemented using a static threshold activation function, limiting the set of learnable functions to be linearly separable. In this work, we propose two NLB designsrobust adaptive NLB (RANLB) and multithreshold NLB (MTNLB)which overcome this limitation by allowing the effective activation function to be adapted during the training process. Consequently, both designs enable any logic function to be implemented in a singlelayer NLB network. The proposed NLBs are designed, simulated, and trained to implement ISCAS85 benchmark circuits, as well as OCR. The MTNLB achieves 90 percent improvement in the energy delay product (EDP) over lookup table (LUT)based implementations of the ISCAS85 benchmarks and up to a 99 percent improvement over a previous NLB implementation. As a compromise, the RANLB provides a smaller EDP improvement, but has an average training time of only ≈ 4 cycles for 4input logic functions, compared to the MTNLBs ≈ 8cycle average training time.
INDEX TERMS
transfer functions, benchmark testing, biocomputing, logic design, memristors, optical character recognition, perceptrons, power aware computing, reconfigurable architectures, table lookup,4input logic functions, memristorbased neural logic blocks, nonlinearly separable functions, biologically inspired reconfigurable hardware realization, perceptronbased NLB designs, thinfilm memristor synapses, static threshold activation function, robust adaptive NLB, RANLB, multithreshold NLB, MTNLB, training process, logic function, singlelayer NLB network, ISCAS85 benchmark circuits, OCR, optical character recognition, multilevel Boolean logic, energy delay product, EDP, lookup table, LUTbased implementations, ISCAS85 benchmarks,Selforganizing networks, Neural networks, Biological system modeling,neural networks, Neuromorphic, stochastic gradient descent, memristors, OCR, reconfigurable logic
CITATION
M. Soltiz, D. Kudithipudi, C. Merkel, G. S. Rose, R. E. Pino, "MemristorBased Neural Logic Blocks for Nonlinearly Separable Functions", IEEE Transactions on Computers, vol.62, no. 8, pp. 15971606, Aug. 2013, doi:10.1109/TC.2013.75
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