The Community for Technology Leaders
RSS Icon
Issue No.08 - Aug. (2013 vol.62)
pp: 1584-1596
James Alfred Walker , University of York, York
Martin A. Trefzer , University of York, York
Simon J. Bale , University of York, York
Andy M. Tyrrell , University of York, York
Field programmable gate arrays (FPGAs) are widely used in applications where online reconfigurable signal processing is required. Speed and function density of FPGAs are increasing as transistor sizes shrink to the nanoscale. As these transistors reduce in size intrinsic variability becomes more of a problem and to reliably create electronic designs according to specification time consuming statistical simulations become necessary; and even with accurate models and statistical simulation, the fabrication yield will decrease as every physical instance of a design behaves differently. This paper describes an adaptive, evolvable architecture that allows for correction and optimization of circuits directly in hardware using bioinspired techniques. Similar to FPGAs, the programmable analog and digital array (PAnDA) architecture introduced provides a digital configuration layer for circuit design. Accessing additional configuration options of the underlying analog layer enables continuous adjustment of circuit characteristics at runtime, which enables dynamic optimization of the mapped design's performance. Moreover, the yield of devices can be improved postfabrication via reconfiguration of the analog layer, which can overcome faults induced due to variability and process defects. Since optimization goals are generic, i.e., not restricted to reducing stochastic variability, power consumption or increasing speed, the same mechanisms can also enhance the device's fault tolerant abilities in the case of component degradation and failures during its lifetime or when exposed to hazardous environments.
Computer architecture, Field programmable gate arrays, Transistors, Optimization, Performance evaluation, Random access memory, Logic gates, adaptive hardware, Reconfigurable architectures, intrinsic variability, bio-inspired algorithms, fault tolerance, evolvable hardware
James Alfred Walker, Martin A. Trefzer, Simon J. Bale, Andy M. Tyrrell, "PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations", IEEE Transactions on Computers, vol.62, no. 8, pp. 1584-1596, Aug. 2013, doi:10.1109/TC.2013.59
[1] G.E. Moore, "Cramming More Components onto Integrated Circuits," Electronics, vol. 38, pp. 114-117, 1965.
[2] A. Asenov, "Variability in the Next Generation CMOS Technologies and Impact on Design," Proc. First Int'l Conf. CMOS Variability, 2007.
[3] G. Declerck, "A Look into the Future of Nanoelectronics," Proc. Symp. VLSI Technology Digest of Technical Papers, pp. 6-10, 2005.
[4] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter Variations and Impact on Circuits and Microarchitecture," Proc. 40th Ann. Design Automation Conf. (DAC), pp. 338-342, 2003.
[5] J.A. Walker, J.A. Hilder, D. Reid, A. Asenov, S. Roy, C. Millar, and A.M. Tyrrell, "The Evolution of Standard Cell Libraries for Future Technology Nodes," Genetic Programming and Evolvable Machines, vol. 12, no. 3, pp. 235-256, Apr. 2011.
[6] A. Asenov, "Statistical Nano CMOS Variability and Its Impact on SRAM," Extreme Statistics in Nanoscale Memory Design, pp. 17-50, 2010.
[7] G. Gielen, E. Maricau, and P. De Wit, "Analog Circuit Reliability in Sub-32 Nanometer CMOS: Analysis and Mitigation," true&arnumber=5763239&contentType=Conference+Publications , 2013.
[8] M. Murakawa, T. Adachi, Y. Niino, Y. Kasai, E. Takahashi, K. Takasuka, and T. Higuchi, "An AI-Calibrated IF Filter: A Yield Enhancement Method with Area and Power Dissipation Reductions," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 495-502, , Mar. 2003.
[9] A. Stoica, R. Zebulum, and D. Keymeulen, "Progress and Challenges in Building Evolvable Devices," Proc. Third NASA/DoD Workshop Evolvable Hardware, p. 33, http://dl.acm.orgcitation.cfm?id=517089.871975 , July 2001.
[10] J. Langeheine, M. Trefzer, J. Schemmel, and K. Meier, "Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip," Proc. NASA/DoD Conf. Evolvable Hardware, pp. 18-25, June 2004.
[11] B. Nikolic and L. teck Pang, "Measurements and Analysis of Process Variability in 90nm CMOS," Proc. Eighth Int'l Conf. Solid-State and Integrated Circuit Technology, pp. 505-508, 2006.
[12] A. Papanikolaou, M. Miranda, H. Wang, F. Catthoor, M. Satyakiran, P. Marchal, B. Kaczer, C. Bruynseraede, and Z. Tokei, "Reliability Issues in Deep Deep Sub-Micron Technologies: Time-Dependent Variability and Its Impact on Embedded System Design," Proc. IFIP Int'l Conf. Very Large Scale Integration, pp. 342-347, arnumber= 4107654 , Oct. 2006.
[13] T. Matsunawa, H. Nosato, H. Sakanashi, M. Murakawa, E. Takahashi, T. Terasawa, T. Tanaka, O. Suga, and T. Higuchi, "Adaptive Optical Proximity Correction Using an Optimization Method," Proc. IEEE Seventh Int'l Conf. Computer and Information Technology (CIT), pp. 853-860, 2007.
[14] V. Kheterpal, V. Rovner, T.G. Hersan, D. Motiani, Y. Takegawa, A.J. Strojwas, and L. Pileggi, "Design Methodology for IC Manufacturability Based on Regular Logic-Bricks," Proc. 42nd Ann. Design Automation Conf., pp. 353-358, 2005.
[15] S. Nassif, K. Bernstein, D.J. Frank, A. Gattiker, W. Haensch, B.L. Ji, E. Nowak, D. Pearson, and N.J. Rohrer, "High Performance CMOS Variability in the 65nm Regime and Beyond," Proc. IEEE Int'l Electron Devices Meeting, pp. 569-571, , 2007.
[16] K. Takeuchi, T. Fukai, T. Tsunomura, A.T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, "Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies," Proc. IEEE Int'l Electron Devices Meeting, pp. 467-470, , 2007.
[17] A. Asenov, S. Kaya, and J.H. Davies, "Intrinsic Threshold Voltage Fluctuations in Decanano MOSFETs due to Local Oxide Thickness Variations," IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 112-119, Jan. 2002.
[18] J.W. Tschanz, J.T. Kao, S.G. Narendra, R. Nair, D.A. Antoniadis, A.P. Chandrakasan, and V. De, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1396-1402, Nov. 2002.
[19] J.B. Bernstein, M. Gurfinkela, X. Lia, J. Waltersa, Y. Shapiraa, and M. Talmora, "Electronic Circuit Reliability Modeling," Microelectronics Reliability, vol. 46, no. 12, pp. 1957-1979, 2006.
[20] J.E. Rubio, M. Jaraiz, I. Martin-Bragado, R. Pinacho, P. Castrillo, and J. Barbolla, "Physically Based Modelling of Damage, Amorphization and Recrystallization for Predictive Device-Size Process Simulation," Materials Science and Eng. B, vol. 114-115, pp. 151-155, 2004.
[21] M. Mizuno and V. De, "Design for Variability in Logic, Memory and Microprocessor," Proc. VLSI Circuits, 2007.
[22] A. Stoica, D. Keymeulen, R.S. Zebulum, A. Thakoor, T. Daud, G. Klimeck, Y. Jin, R. Tawel, and V. Duong, "Evolution of Analog Circuits on Field Programmable Transistor Arrays," Proc. Second NASA/DOD Workshop Evolvable Hardware, pp. 99-108, July 2000.
[23] J. Langeheine, J. Becker, S. Fölling, K. Meier, and J. Schemmel, "A CMOS FPTA Chip for Intrinsic Hardware Evolution of Analog Electronic Circuits," Proc. Third NASA/DOD Workshop Evolvable Hardware, pp. 172-175, July 2001.
[24] M.A. Trefzer, "Evolution of Transistor Circuits," PhD dissertation, Rupertus Carola Univ. of Heidelberg, Seminarstrasse 2, 69120 Heidelberg, Dec. 2006.
[25] J.A. Walker, R. Sinnott, G. Stewart, J.A. Hilder, and A.M. Tyrrell, "Optimizing Electronic Standard Cell Libraries for Variability Tolerance through the Nano-CMOS Grid," Philosophical Transactions, Series A, Math., Physical, and Eng. Sciences, vol. 368, no. 1925, pp. 3967-3981, cgi/ content/abstract/368/19253967, Aug. 2010.
[26] M.A. Trefzer, J.A. Walker, and A.M. Tyrrell, "A Programmable Analog and Digital Array for Bio-Inspired Electronic Design Optimization at Nano-Scale Silicon Technology Nodes," Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, Nov. 2011.
[27] Gold Standard Simulations Ltd (GSS), "RandomSpice," circuit-simulationrandom-spice/, 2010.
[28] ngenics Ltd, "MOTIVATED," http://www.ngenics.comservices, 2012.
18 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool