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Issue No.08 - Aug. (2013 vol.62)
pp: 1481-1493
R. Salvador , Dept. de Sist. Electronicos y de Control, Univ. Politec. de Madrid, Madrid, Spain
A. Otero , Centro de Electron. Ind., Univ. Politec. de Madrid, Madrid, Spain
J. Mora , Centro de Electron. Ind., Univ. Politec. de Madrid, Madrid, Spain
E. de la Torre , Centro de Electron. Ind., Univ. Politec. de Madrid, Madrid, Spain
T. Riesgo , Centro de Electron. Ind., Univ. Politec. de Madrid, Madrid, Spain
L. Sekanina , IT4Innovations Centre of Excellence, Brno Univ. of Technol., Brno, Czech Republic
ABSTRACT
This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means of dynamic partial reconfiguration, enabling evaluation in the final hardware. The PE array follows a systolic approach, and PEs do not contain extra logic such as path multiplexers or unused logic, so array performance is high. Hardware evaluation in the target device and the fast reconfiguration engine used yield smaller reconfiguration than evaluation times. This means that the complete evaluation cycle is faster than software-based approaches and previous evolvable digital systems. The selected application is digital image filtering and edge detection. The evolved filters yield better quality than classic linear and nonlinear filters using mean absolute error as standard comparison metric. Results do not only show better circuit adaptation to different noise types and intensities, but also a nondegrading filtering behavior. This means they may be run iteratively to enhance filtering quality. These properties are even kept for high noise levels (40 percent). The system as a whole is a step toward fully autonomous, adaptive systems.
INDEX TERMS
systolic arrays, edge detection, field programmable gate arrays, filtering theory, genetic algorithms, image denoising, image enhancement, iterative methods, reconfigurable architectures,genetic algorithm, self-reconfigurable evolvable hardware system, adaptive image processing, FPGA, autonomous digital processing circuit generation, processing elements, PE array, candidate circuits, embedded evolutionary algorithm, dynamic partial reconfiguration, systolic approach, hardware evaluation, evaluation cycle, digital image filtering, edge detection, mean absolute error, noise types, intensities, nondegrading filtering behavior, filtering quality enhancement, autonomous systems, adaptive systems,Evolutionary computing, Genetic algorithms, Self-organizing networks,evolutionary computing and genetic algorithms, Evolvable hardware, FPGAs, self-adaptive systems, reconfigurable hardware, adaptable architectures, autonomous systems
CITATION
R. Salvador, A. Otero, J. Mora, E. de la Torre, T. Riesgo, L. Sekanina, "Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing", IEEE Transactions on Computers, vol.62, no. 8, pp. 1481-1493, Aug. 2013, doi:10.1109/TC.2013.78
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