The Community for Technology Leaders
RSS Icon
Issue No.06 - June (2013 vol.62)
pp: 1111-1126
Salvatore Pontarelli , University of Rome, Rome
Marco Ottavi , University of Rome, Rome
A content addressable memory (CAM) is an SRAM-based memory that can be accessed in parallel to search for a given search word, providing as a result the address of the matching data. Like conventional memories, a CAM can be affected by the occurrence of single event upsets (SEUs) that can alter the content of one of more memory cells causing different effects such as pseudo-HIT or pseudo-MISS events. It is well known that, because of the parallel search performed by a CAM during the query of a word, a standard error correction code could not defend it against SEU events. In this paper, we propose a method that does not require any modification to a CAM's internal structure and, therefore, can be easily applied at system level. Error detection is performed by using a probabilistic structure called "Bloom filter,” which can signal if a given data is present in the CAM. Bloom filters permit to efficiently store and query the presence of data in a set. But, while a CAM suffers from SEU induced errors, the probabilistic nature of Bloom filters has as a consequence the so called false-positive effect. This paper shows that, by combining the use of a Bloom filter with a CAM, the complementary limitations of these modules can be compensated. The combined use of a CAM and a Bloom filter is analyzed in different cases, showing that the proposed technique can be implemented with a low penalty in terms of area and power consumption.
Computer aided manufacturing, Random access memory, Error correction codes, Single event upset, Power demand, Associative memory, Arrays, error detection and correction, Bloom filter, content addressable memories
Salvatore Pontarelli, Marco Ottavi, "Error Detection and Correction in Content Addressable Memories by Using Bloom Filters", IEEE Transactions on Computers, vol.62, no. 6, pp. 1111-1126, June 2013, doi:10.1109/TC.2012.56
[1] N. Kanekawa, E.H. Ibe, T. Suga, and Y. Uematsu, Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and Electro-Magnetic Disturbances. Springer Verlag, 2010.
[2] G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, and A. Salsano, "A Fault-Tolerant Solid State Mass Memory for Space Applications," IEEE Trans. Aerospace and Electronic Systems, vol. 41, no. 4, pp. 1353-1372, Oct. 2005.
[3] W.W. Peterson and E.J. Weldon, Error-Correcting Codes. The MIT Press, 1972.
[4] T. Yamagata, M. Mihara, T. Hamamoto, Y. Murai, T. Kobayashi, M. Yamada, and H. Ozaki, "A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1927-1933, Dec. 1992.
[5] L. Chisvin and R.J. Duckworth, "Content-Addressable and Associative Memory: Alternatives to the Ubiquitous RAM," IEEE Computer, vol. 22, no. 7, pp. 51-64, July 1989.
[6] V. Lines, A. Ahmed, P. Ma, S. Ma, R. McKenzie, H-S. Kim, and C. Mar, "66 MHz 2.3 M Ternary Dynamic Content Addressable Memory," Proc. IEEE Int'l Workshop Memory Technology, Design Testing, pp. 101-105, 2000.
[7] N. Azizi and F.N. Najm, "A Family of Cells to Reduce the Soft-Error-Rate in Ternary-CAM," Proc. 43rd Ann. Design Automation Conf., 2006.
[8] S.C. Krishnan, R. Panigrahy, and S. Parthasarathy, "Error-Correcting Codes for Ternary Content Addressable Memories," IEEE Trans. Computers, vol. 58, no. 2, pp. 275-279, Feb. 2009.
[9] F. Salice, M.G. Sami, and R. Stefanelli, "Fault-Tolerant CAM Architectures: A Design Framework," Proc. IEEE 17th Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT '02), pp. 233-241, Oct. 2002.
[10] A. Bremler-Barr, D. Hay, D. Hendler, and R.M. Roth, "PEDS: A Parallel Error Detection Scheme for TCAM Devices," IEEE/ACM Trans. Networking, vol. 18, no. 5, pp. 1665-1675, Oct. 2010.
[11] C. Wan, J. Lan, and Y. Hu, "Lookup with CAM Aided Hash Table," Proc. IEEE Int'l Conf. Frontier of Computer Science and Technology, 2009.
[12] J. Peir, S. Lai, S. Lu, J. Stark, and K. Lai, "Bloom Filtering Cache Misses for Accurate Data Speculation and Prefetching," Proc. 16th Int'l Conf. Supercomputing (ICS '02).
[13] M. Ghosh, E. Ozer, S. Ford, S. Biles, and H.S. Lee, "Way Guard: A Segmented Counting Bloom Filter Approach to Reducing Energy for Set-Associative Caches," Proc. ACM/IEEE 14th Int'l Symp. Low Power Electronics and Design (ISLPED '09), 2009.
[14] K. Pagiamtzis and A. Sheikholeslami, "Content Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006.
[15] D.A. Patterson and J.L. Hennessy, Computer Architecture: A Quantitative Approach, third ed. Morgan Kaufmann, 2003.
[16] H. Chao, "Next Generation Routers," Proc. IEEE, vol. 90, no. 9, pp. 1518-1558, Sept. 2002.
[17] S. Satoh, Y. Tosaka, and S.A. Wender, "Geometric Effect of Multiple-Bit Soft Errors Induced by Cosmic Ray Neutrons On DRAMs," IEEE Electron Device Letter, vol. 21, no. 6, pp. 310-312, June 2000.
[18] P. Reviriego, J.A. Maestro, S. Baeg, S.J. Wen, and R. Wong, "Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance," IEEE Trans. Nuclear Science, vol. 57, no. 4, pp. 2124-2128, Aug. 2010.
[19] N. Seifert, B. Gill, K. Foley, and P. Relangi, "Multi-Cell Upset Probabilities of 45nm High-K $+$ Metal Gate SRAM Devices in Terrestrial and Space Environments," Proc. IEEE Int'l Reliability Physics Symp. (IRPS '08), pp. 181-186, 2008.
[20] H. Noda et at., "A Cost-Efficient High-Performance Dynamic TCAM with Pipelined Hierarchical Search and Shift Redundancy Architecture," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 245-253, Jan. 2005.
[21] H. Noda, K. Dosaka, F. Morishita, and K. Arimoto, "A Soft-Error Immune Maintenance-Free TCAM Architecture with Associated Embedded DRAM," Proc. IEEE Custom Integrated Circuits Conf., pp. 451-454, Sept. 2005.
[22] K. Pagiamtzis, N. Azizi, and F.N. Najm, "A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme," Proc. IEEE Custom Integrated Circuits Conf., 2006.
[23] A.K. Somani and S. Kim, "Transient Fault Detection in Cache Memories by Employing a Small Shadow Cache," Proc. Dependable Computing for Critical Applications Conf., pp. 19-39, 1998.
[24] A. Hossein, S. Vilas, M.B. Tahoori, and D. Kaeli, "Vulnerability Analysis of L2 Cache Elements to Single Event Upsets," Proc. IEEE Design, Automation and Test in Europe (DATE '06), pp. 1-6, 2006.
[25] W. Zhang, "Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability" IEEE Trans. Computers, vol. 54, no. 12, pp. 1547-1555, Dec. 2005.
[26] H. Sun, N. Zheng, and T. Zhang, "Realization of L2 Cache Defect Tolerance Using Multi-Bit ECC," Proc. IEEE 23th Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT '08), pp. 254-262, Oct. 2008.
[27] S. Kim and A.K. Somani, "Area Efficient Architectures for Information Integrity in Cache Memories," Proc. Int'l Symp. Computer Architecture (ISCA '99), pp. 246-255, May 1999.
[28] H. Asadi, V. Sridharan, M. Tahoori, and D. Kaeli, "Reliability Tradeoffs in Design of Cache Memories," Proc. First Workshop Architectural Reliability, 2005.
[29] H.J. Lee, "Immediate Soft Error Detection Using Pass Gate Logic for Content Addressable Memory," Electronics Letters, vol. 44, no. 4, pp. 269-270, 2008.
[30] S. Pontarelli, M. Ottavi, and A. Salsano, "Error Detection and Correction in Content Addressable Memories," Proc. IEEE 25th Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT '10), Oct. 2010.
[31] B. Bloom, "Space/Time Tradeoffs in Hash Coding with Allowable Errors," Comm. ACM, vol. 13, no. 7, pp. 422-426, 1970.
[32] L. Fan, P. Cao, J. Almeida, and A. Broder, "Summary Cache: A Scalable Wide-Area Web Cache Sharing Protocol," IEEE/ACM Trans. Networking, vol. 8, no. 3, pp. 281-293, 1998.
[33] C. Estan and G. Varghese, "New Directions in Traffic Measurement and Accounting," ACM SIGCOMM, vol. 32, no. 4, pp. 323-336, Oct. 2002.
[34] S. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Technical Report 93/5, DEC Western Research Laboratory, 1994.
[35] B. Agrawal and T. Sherwood, "Ternary CAM Power and Delay Model: Extensions and Uses," IEEE Trans. Very Large Scale Integration Systems, vol. 16, no. 5, pp. 554-564, May 2008.
[36] B. Agrawal and T. Sherwood, "Modeling TCAM Power for Next Generation Network Devices," Proc. Int'l Symp. Performance Analysis of Systems and Software (ISPASS '06), pp. 120-129, 2006.
[37] H. Vandierendonck and K. De Bosschere, "XOR-Based Hash Functions," IEEE Trans. Computers, vol. 54, no. 7, pp. 800-812, July 2005.
[38] J.L. Henning, "SPEC CPU2000: Measuring CPU Performance in the New Millennium," IEEE Computer, vol. 33, no. 7, pp. 28-35, July 2000.
[39] T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling," IEEE Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
[40] A. Kirsch and M. Mitzenmacher, "Less Hashing, Same Performance: Building a Better Bloom Filter," Proc. 14th Ann. European Symp. Algorithms (ESA '06), pp. 456-467, 2006.
[41] Cisco Catalyst 6500 Series Switches Data Sheet, http://www. switches/ps708products_ data_sheets_list.html , 2012.
56 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool