The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.04 - April (2013 vol.62)
pp: 832-838
Jui-Chieh Lin , Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA
Sao-Jie Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Yu Hen Hu , Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA
ABSTRACT
Cycle-efficient implementation of the linear feedback shift register (LFSR) algorithm on a word-based microarchitecture is investigated. This work examines an algorithm transformation method, called term-preserving look-ahead transformation (TePLAT), that transforms the bit-serial LFSR algorithm into a bit parallel format while maintaining the overhead of the original LFSR algorithm. Detailed implementation methodologies as well as extensive simulation results are presented. We apply TePLAT to 25 commonly used LFSRs and test the resulting parallel formulations on two popular word-based microprocessor development platforms: a Texas Instrument C6416 Code Composition Simulator and an ARM-9 Simulator. In all 25 cases, TePLAT transformed LFSR formulations consistently achieve much higher throughput than those of a naïve implementation and a traditional look-ahead transformation-based implementation.
INDEX TERMS
software radio, microprocessor chips, shift registers, software defined radio, cycle-efficient LFSR implementation, word-based microarchitecture, linear feedback shift register algorithm, algorithm transformation method, term-preserving look-ahead transformation, TePLAT, bit-serial LFSR algorithm, bit parallel format, word-based microprocessor development platforms, Texas Instrument C6416 code composition simulator, ARM-9 simulator, look-ahead transformation-based implementation, Polynomials, Generators, Throughput, Registers, Parallel processing, Vectors, software defined radio, Linear feedback shift register, iteration bound, vector processing, look-ahead transformation
CITATION
Jui-Chieh Lin, Sao-Jie Chen, Yu Hen Hu, "Cycle-Efficient LFSR Implementation on Word-Based Microarchitecture", IEEE Transactions on Computers, vol.62, no. 4, pp. 832-838, April 2013, doi:10.1109/TC.2012.14
REFERENCES
[1] J. MitolaIII, Cognitive Radio Architecture. John Wiley & Sons, 2006.
[2] J. Glossner et al., "A Software-Defined Communications Baseband Design," Proc. IEEE Comm. Magazine, vol. 41, no. 1, pp. 120-128, 2003.
[3] H. Lee and T. Mudge, "A Dual-Processor Solution for the MAC Layer of a Software Defined Radio Terminal," Proc. Int'l Conf. Compilers, Architecture and Synthesis for Embedded Systems (CASE '05), no. 7, pp. 257-265, 2005.
[4] IEEE Std. 802.11-2007, Part 11, "Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications," 2007.
[5] G.C. Ahlquist, M. Rice, and B. Nelson, "Error Control Coding in Software Radios: An FPGA Approach," Proc. IEEE Personal Comm., vol. 6, no. 4, pp. 35-39, Aug. 1999.
[6] V. Sriram and D. Kearney, "An FPGA Implementation of a Parallelized MT19937 Uniform Random Number Generator," EURASIP J. Embedded Systems, vol. 2009, no. 7, pp. 1-6, 2009.
[7] K.K. Saluja and C.-F. See, "An Efficient Signature Computation Method," IEEE Design and Test of Computers, vol. 9, no. 4, pp. 22-26, Dec. 1992.
[8] S.H. Jeong, M.H. Sunwoo, and S.K. Oh, "Bit Manipulation Accelerator for Communication Systems Digital Signal Processor," EURASIP J. Applied Signal Processing, vol. 2005, no. 16, pp. 2655-2663, 2005.
[9] M. Wei, M. Snir, J. Torrellas, and R.B. Tremaine, "A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads," Proc. Second Watson Conf. Interaction between Architecture, Circuits, and Compilers, 2005.
[10] K.K. Parhi, VLSI Digital Signal Processing Systems Design and Implementation. John Wiley & Sons, Inc., 1999.
[11] Y. Tang, L. Qian, and Y. Wang, "Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor," Proc. IEEE Global Comm. Conf. (GLOBECOM '05), vol. 4, pp. 2194-2198, 2005.
[12] S. Chowdhury and S. Maitra, "Efficient Software Implementation of Linear Feedback Shift Registers," Proc. Second Int'l Conf. Cryptology in India: Progress in Cryptology (INDOCRYPT '01 ), vol. 2247, pp. 297-307, 2001.
[13] C. Lauradoux, "From Hardware to Software Synthesis of Linear Feedback Shift Registers," Proc. IEEE 21st Int'l Parallel and Distributed Processing Symp. (IPDPS '07), pp. 1-8, 2007.
[14] S. Sriram and V. Sundararajan, "Efficient Pseudo-Noise Sequence Generation for Spread-Spectrum Applications," Proc. IEEE Workshop Signal Processing Systems (SIPS '02), pp. 80-86, 2002.
[15] J. Lin et al., "Cycle Efficient Scrambler Implementation for Software Defined Radio," Proc. Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP '10), pp. 1586-1589, 2010.
[16] Texas Instruments, Code Composer Studio Development Tools v3.3 Getting Started Guide, SPRU509H, 2008.
[17] ARM Limited, Realview ARMulator ISS User Guide v1.4.3, ARM DUI 0207D, 2007.
[18] R. Lidl and H. Niederreiter, "Introduction to Finite Fields and Their Applications," revised ed. Cambridge Univ. Press, 1994.
[19] R.S. Katti, X. Ruan, and H. Khattri, "Multiple-Output Low-Power Linear Feedback Shift Register Design," IEEE Trans. Circuits and System I, vol. 53, no. 7, pp. 1487-1495, July 2006.
[20] IEEE Std. 802.16e-2005, Part 16: Air Interface for Fixed Broadband Wireless Access Systems, IEEE Std. 802.16, 2006.
[21] 3GPP TS 36.212 v8.4.0, "Multiplexing and Channel Coding," 2008.
[22] F. Didier and L. Yann, "Finding Low-Weight Polynomial Multiples Using Discrete Logarithm," Proc. IEEE Int'l Symp. Information Theory (ISIS '07), pp. 1036-1040, 2007.
[23] M. Hell, T. Johansson, and W. Meier, "Grain—A Stream Cipher for Constrained Environment," Int'l J. Wireless and Mobile Computing, vol. 2, no. 1, pp. 86-93, 2007.
[24] C.G. Günther, "Parallel Generation of Recurring Sequences," Proc. Advances in Cryptology, pp. 503-522, 1989.
59 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool