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Issue No.04 - April (2013 vol.62)
pp: 730-743
Sourav Sen Gupta , Indian Stat. Inst., ASU, Kolkata, India
A. Chattopadhyay , UMIC Res. Centre, RWTH Aachen Univ., Aachen, Germany
K. Sinha , Hewlett Packard Labs., Bangalore, India
S. Maitra , Indian Stat. Inst., ASU, Kolkata, India
B. P. Sinha , Indian Stat. Inst., ACMU, Kolkata, India
RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces 2 RC4 keystream bytes per clock cycle. We have optimized and implemented our proposed design using VHDL description, synthesized with 130, 90, and 65 nm fabrication technologies at clock frequencies 625 MHz, 1.37 GHz, and 1.92 GHz, respectively, to obtain a final RC4 keystream throughput of 10, 21.92, and 30.72 Gbps in the respective technologies.
hardware description languages, cryptography, frequency 1.92 GHz, RC4 stream cipher, cryptology domain, VHDL description, Verilog high scale description language, RC4 keystream throughput, size 130 nm, size 90 nm, size 65 nm, frequency 625 MHz, frequency 1.37 GHz, Hardware, Registers, Throughput, Adders, Clocks, Pipeline processing, Computer architecture, stream cipher, Cryptography, hardware accelerator, high throughput, loop unrolling, pipelining, RC4
Sourav Sen Gupta, A. Chattopadhyay, K. Sinha, S. Maitra, B. P. Sinha, "High-Performance Hardware Implementation for RC4 Stream Cipher", IEEE Transactions on Computers, vol.62, no. 4, pp. 730-743, April 2013, doi:10.1109/TC.2012.19
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