Issue No.02 - Feb. (2013 vol.62)
Wei Zang , University of Florida, Gainesville
Ann Gordon-Ross , University of Florida, Gainesville
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.194
The cache hierarchy's large contribution to total microprocessor system power makes caches a good optimization candidate. To facilitate a fast design-time cache optimization process, we propose a single-pass trace-driven cache simulation methodology—T-SPaCS—for a two-level exclusive cache hierarchy. Direct adaptation of conventional trace-driven cache simulation to two-level caches requires significant storage and simulation time as numerous stacks record cache access patterns for each level one and level two cache combination and each stack is repeatedly processed. T-SPaCS significantly reduces storage space and simulation time using a set of stacks that only record the complete cache access pattern. Thereby, T-SPaCS simulates all cache configurations for both the level one and level two caches simultaneously in a single pass. Experimental results show that T-SPaCS is 21.02X faster on average than sequential simulation for instruction caches and 33.34X faster for data caches. A simplified, but minimally lossy version of T-SPaCS (simplified-T-SPaCS) increases the average simulation speedup to 30.15X for instruction caches and 41.31X for data caches. We leverage T-SPaCS and simplified-T-SPaCS for determining the lowest energy cache configuration to quantify the effects of lossiness and observe that T-SPaCS and simplified-T-SPaCS still find the lowest energy cache configuration as compared to exact simulation.
Tuning, Algorithm design and analysis, Computational modeling, Analytical models, Complexity theory, Data models, Program processors, simulation, Cache memories, low-power design, real-time systems and embedded systems
Wei Zang, Ann Gordon-Ross, "T-SPaCS—A Two-Level Single-Pass Cache Simulation Methodology", IEEE Transactions on Computers, vol.62, no. 2, pp. 390-403, Feb. 2013, doi:10.1109/TC.2011.194