The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.02 - Feb. (2013 vol.62)
pp: 295-309
George Michelogiannakis , Stanford University, Stanford
William J. Dally , Stanford University, Stanford
ABSTRACT
Networks-on-chip (NoCs) were developed to meet the communication requirements of large-scale systems. The majority of current NoCs spend considerable area and power for router buffers. In our past work, we have developed elastic buffer (EB) flow control which adds simple control logic in the channels to use pipeline flip-flops (FFs) as EBs with two storage locations. This way, channels act as distributed FIFOs and input buffers are no longer required. Removing buffers and virtual channels (VCs) significantly simplifies router design. Compared to VC networks with highly-efficient custom SRAM buffers, EB networks provide an up to 45 percent shorter cycle time, 16 percent more throughput per unit power, or 22 percent more throughput per unit area. EB networks provide traffic classes using duplicate physical subnetworks. However, this approach negates the cost gains or becomes infeasible for a large number of traffic classes. Therefore, in this paper we propose a hybrid EB-VC router which provides an arbitrary number of traffic classes by using an input buffer to drain flits facing severe contention or deadlock. Thus, hybrid routers operate as EB routers in the common case, and as VC routers when necessary. For this reason, the hybrid EB-VC scheme offers 21 percent more throughput per unit power than VC networks and 12 percent than EB networks.
INDEX TERMS
Switches, Throughput, Radiation detectors, Latches, Routing, Pipeline processing, interconnection architectures, On-chip interconnection networks
CITATION
George Michelogiannakis, William J. Dally, "Elastic Buffer Flow Control for On-Chip Networks", IEEE Transactions on Computers, vol.62, no. 2, pp. 295-309, Feb. 2013, doi:10.1109/TC.2011.237
REFERENCES
[1] W.J. Dally and B. Towles, “Route Packets Not Wires: On-Chip Interconnection Networks,” Proc. 38th Ann. Design Automation Conf. (DAC '01), 2001.
[2] M.B. Taylor et al., “Evaluation of the RAW Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,” Proc. 31st Ann. Int'l Symp. Computer Architecture (ISCA '04), p. 2, 2004.
[3] P. Gratz, C. Kim, R. McDonald, S. Keckler, and D. Burger, “Implementation and Evaluation of On-Chip Network Architectures,” Proc. Int'l Conf. Computer Design (ICCD '06), pp. 477-484, 2006.
[4] A.B. Kahng, B. Li, L.-S. Peh, and K. Samadi, “Orion 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration,” Proc. 46th Ann. Conf. Design Automation (DAC '09), pp. 423-428, 2009.
[5] J. Balfour and W.J. Dally, “Design Tradeoffs for Tiled CMP On-Chip Networks,” Proc. 20th Ann. Int'l Conf. Supercomputing (ISCA '06), 2006.
[6] G. Michelogiannakis, J. Balfour, and W.J. Dally, “Elastic Buffer Flow Control for On-Chip Networks,” Proc. IEEE 15th Int'l Symp. High-Performance Computer Architecture (HPCA '09), pp. 151-162, 2009.
[7] R. Mullins, A. West, and S. Moore, “Low-Latency Virtual-Channel Routers for On-Chip Networks,” Proc. 31st Ann. Int'l Symp. Computer Architecture (ISCA '04), p. 188, 2004.
[8] G. Michelogiannakis and W.J. Dally, “Router Designs for Elastic Buffer On-Chip Networks,” Proc. Conf. High Performance Computing Networking, Storage and Analysis (SC '09), pp. 1-10, 2009.
[9] G. Michelogiannakis, D. Becker, and W. Dally, “Evaluating Elastic Buffer and Wormhole Flow Control,” IEEE Trans. Computers, vol. 60, no. 6, pp. 896-903, June 2011.
[10] M. Galles, “Spider: A High-Speed Network Interconnect,” IEEE Micro, vol. 17, no. 1, pp. 34-39, Jan./Feb. 1997.
[11] T. Bjerregaard and S. Mahadevan, “A Survey of Research and Practices of Network-on-Chip,” ACM Computing Surveys, vol. 38, no. 1, p. 1, 2006.
[12] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, Inc., 2003.
[13] F. Gilabert, M.E. Gomez, S. Medardoni, and D. Bertozzi, “Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-Processor Systems-on-Chip,” Proc. IEEE/ACM Fourth Int'l Symp. Networks-on-Chip (NOCS '10), pp. 165-172, 2010.
[14] L. Ni and P. McKinley, “A Survey of Wormhole Routing Techniques in Direct Networks,” Readings in Computer Architecture, pp. 492-506, Gulf Professional Publishing, 2000.
[15] A. Singh, “Load-Balanced Routing in Interconnection Networks,” PhD in Electrical Eng., Stanford Univ., 2005.
[16] J. Kim, W.J. Dally, and D. Abts, “Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks,” Proc. 34th Ann. Int'l Symp. Computer Architecture (ISCA '07), 2007.
[17] J. Kim, W.J. Dally, S. Scott, and D. Abts, “Technology-Driven, Highly-Scalable Dragonfly Topology,” Proc. 35th Ann. Int'l Symp. Computer Architecture (ISCA '08), pp. 77-88, 2008.
[18] H. Wang, L.-S. Peh, and S. Malik, “Power-Driven Design of Router Microarchitectures in On-Chip Networks,” Proc. IEEE/ACM 36th Ann. Int'l Symp. Microarchitecture (MICRO '03), 2003.
[19] R. Ho, K. Mai, and M. Horowitz, “Efficient On-Chip Global Interconnects,” Proc. Symp. VLSI Circuits, pp. 271-274, 2003.
[20] M. Mizuno, W.J. Dally, and H. Onishi, “Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data,” Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC '01), pp. 346-347, 2001.
[21] G. Michelogiannakis, D. Sanchez, W.J. Dally, and C. Kozyrakis, “Evaluating Bufferless Flow Control for On-chip Networks,” Proc. IEEE/ACM Fourth Int'l Symp. Networks-on-Chip (NOCS '10), pp. 9-16, 2010.
[22] J. Cortadella, M. Kishinevsky, and B. Grundmann, “Synthesis of Synchronous Elastic Architectures,” Proc. IEEE/ACM 43rd Ann. Design Automation Conf. (DAC '06), pp. 657-662, 2006.
[23] H. Jacobson et al., “Synchronous Interlocked Pipelines,” Proc. Eighth Int'l Symp. Asynchronous Circuits and Systems, pp. 3-12, 2002.
[24] L.P. Carloni, “The Role of Back-Pressure in Implementing Latency-Insensitive Systems,” Electronic Notes in Theoretical Computer Science, vol. 146, pp. 61-80, 2006.
[25] D. Harris and T.P.S.U.C. Archives, “Local Stall Propagation,” http://citeseer.ist.psu.edu506008.html, 2000.
[26] N. Concer, M. Petracca, and L.P. Carloni, “Distributed Flit-buffer Flow Control for Networks-on-Chip,” Proc. IEEE/ACM/IFIP Sixth Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '08), pp. 215-220, 2008.
[27] A. Kodi, A. Sarathy, and A. Louri, “Design of Adaptive Communication Channel Buffers for Low-Power Area-Efficient Network-on-Chip Architecture,” Proc. Third Symp. Architecture for Networking and Comm. systems (ANCS '07), pp. 47-56, 2007.
[28] J.H. Kim, Z. Liu, and A.A. Chien, “Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing,” SIGARCH Computer Architecture News, vol. 22, no. 2, pp. 289-300, 1994.
[29] J. Liu, L.-R. Zheng, and H. Tenhunen, “A Guaranteed-Throughput Switch for Network-on-Chip,” Proc. Int'l Symp. System-on-Chip (SOC '03), pp. 31-34, 2003.
[30] D. Wiklund and D. Liu, “SoCBUS: Switched Network-on-Chip for Hard Real Time Embedded Systems,” Proc. 17th Int'l Symp. Parallel and Distributed Processing (IPDPS '03), p. 8, 2003.
[31] Y. Turner and Y. Tamir, “Deadlock-Free Connection-Based Adaptive Routing with Dynamic Virtual Circuits,” J. Parallel and Distributed Computing, vol. 67, no. 1, pp. 13-32, 2007.
[32] T. Moscibroda and O. Mutlu, “A Case for Bufferless Routing in On-Chip Networks,” SIGARCH Computer Architecture News, vol. 37, no. 3, pp. 196-207, 2009.
[33] Z. Lu, M. Zhong, and A. Jantsch, “Evaluation of On-Chip Networks Using Deflection Routing,” Proc. 16th ACM Great Lakes Symp. VLSI (GLSVLSI), 2006.
[34] C. Gómez, M.E. Gómez, P. López, and J. Duato, “Reducing Packet Dropping in a Bufferless NoC,” Proc. 14th Int'l Euro-Par Conf. Parallel Processing, 2008.
[35] M. Hayenga, N.E. Jerger, and M. Lipasti, “Scarab: A Single Cycle Adaptive Routing and Bufferless Network,” Proc. IEEE/ACM 42nd Ann. Int'l Symp. Microarchitecture (MICRO '42), pp. 244-254, 2009.
[36] P. Gratz, B. Grot, and S. Keckler, “Regional Congestion Awareness for Load Balance in Networks-on-Chip,” Proc. IEEE 14th Int'l Symp. High-Performance Computer Architecture (HPCA '08), pp. 203 -214, 2008.
[37] L.-S. Peh and W.J. Dally, “Flit-Reservation Flow Control,” Proc. Sixth Int'l Symp. High-Performance Computer Architecture (HPCA '00), 2000.
39 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool