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Efficient hardware implementations of brw polynomials and tweakable enciphering schemes
Feb. 2013 (vol. 62 no. 2)
pp. 279-294
D. Chakraborty, Comput. Sci. Dept., CINVESTAV-IPN, Mexico City, Mexico
C. Mancillas-Lopez, Comput. Sci. Dept., CINVESTAV-IPN, Mexico City, Mexico
F. Rodriguez-Henriqueźquez, Comput. Sci. Dept., CINVESTAV-IPN, Mexico City, Mexico
P. Sarkar, Appl. Stat. Unit, Indian Stat. Inst., Kolkata, India
A new class of polynomials was introduced by Bernstein (Bernstein 2007) which were later named by Sarkar as BernsteinRabin-Winograd (BRW) polynomials (Sarkar 2009). For the purpose of authentication, BRW polynomials offer considerable computational advantage over usual polynomials: (m - 1) multiplications for usual polynomial hashing versus ⌊m/2⌋ multiplications and ⌈log2 m⌉ squarings for BRW hashing, where m is the number of message blocks to be authenticated. In this paper, we develop an efficient pipelined hardware architecture for computing BRW polynomials. The BRW polynomials have a nice recursive structure which is amenable to parallelization. While exploring efficient ways to exploit the inherent parallelism in BRW polynomials we discover some interesting combinatorial structural properties of such polynomials. These are used to design an algorithm to decide the order of the multiplications which minimizes pipeline delays. Using the nice structural properties of the BRW polynomials we present a hardware architecture for efficient computation of BRW polynomials. Finally, we provide implementations of tweakable enciphering schemes proposed in Sarkar 2009 which use BRW polynomials. This leads to the fastest known implementation of disk encryption systems.
Index Terms:
polynomials,cryptographic protocols,message authentication,TES,hardware implementations,BRW polynomials,Bernstein-Rabin-Winograd polynomials,message block authentication,pipelined hardware architecture,recursive structure,parallelization,inherent parallelism,combinatorial structural properties,pipeline delay minimization,tweakable enciphering schemes,disk encryption systems,Polynomials,Hardware,Clocks,Frequency modulation,Vegetation,Encryption,Computer architecture,polynomial evaluation,Pipelined architecture,tweakable enciphering schemes,Karatsuba multiplier,disc encryption
Citation:
D. Chakraborty, C. Mancillas-Lopez, F. Rodriguez-Henriqueźquez, P. Sarkar, "Efficient hardware implementations of brw polynomials and tweakable enciphering schemes," IEEE Transactions on Computers, vol. 62, no. 2, pp. 279-294, Feb. 2013, doi:10.1109/TC.2011.227
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