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Issue No.02 - Feb. (2013 vol.62)
pp: 242-246
K. Balston , Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
M. Karimibiuki , Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
A. J. Hu , Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
S. J. E. Wilton , Dept. of Comput. Sci., Univ. of British Columbia, Vancouver, BC, Canada
ABSTRACT
Effective techniques for post-silicon validation are required to better evaluate functional correctness of increasingly complex multi and many-core SoCs. However, there is little data evaluating the coverage of post-silicon validation efforts on industrial-scale designs. In this paper, we address this knowledge gap by instrumenting a nontrivial SoC with on-chip coverage monitors to measure the coverage achieved by typical post-silicon validation tests, such as booting the operating system (OS). We compare coverage achieved pre and post-silicon, and also measure the area overhead required to monitor post-silicon coverage. Our results show that the typical test of booting the OS often achieves high coverage, well correlated to what is achieved by pre-silicon directed tests, but in some blocks the coverage can be low or markedly different between pre and post-silicon, highlighting the importance of post-silicon validation in general and post-silicon coverage measurement in particular.
INDEX TERMS
System-on-a-chip, Monitoring, Central Processing Unit, Instruments, Silicon, IP networks, Booting,code coverage, FPGA emulation, pre-silicon validation, post-silicon validation
CITATION
K. Balston, M. Karimibiuki, A. J. Hu, A. Ivanov, S. J. E. Wilton, "Post-silicon code coverage for multiprocessor system-on-chip designs", IEEE Transactions on Computers, vol.62, no. 2, pp. 242-246, Feb. 2013, doi:10.1109/TC.2012.163
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