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Issue No.02 - Feb. (2013 vol.62)
pp: 225-241
Luigi Di Guglielmo , University of Verona, Verona
Franco Fummi , University of Verona, Verona and EDALab, Verona
Graziano Pravadelli , University of Verona, Verona and EDALab, Verona
Francesco Stefanni , University of Verona, Verona and EDALab, Verona
Sara Vinco , University of Verona, Verona
Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univer CM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univer CM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univer CM in managing system heterogeneity.
Automata, Valves, Semantics, Computational modeling, Syntactics, Delay, Wires, multiprocessor, Formal specifications, modeling, simulation, electronic design automation
Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Sara Vinco, "UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration", IEEE Transactions on Computers, vol.62, no. 2, pp. 225-241, Feb. 2013, doi:10.1109/TC.2012.156
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