Subscribe

Issue No.02 - Feb. (2013 vol.62)

pp: 225-241

Luigi Di Guglielmo , University of Verona, Verona

Franco Fummi , University of Verona, Verona and EDALab, Verona

Graziano Pravadelli , University of Verona, Verona and EDALab, Verona

Francesco Stefanni , University of Verona, Verona and EDALab, Verona

Sara Vinco , University of Verona, Verona

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.156

ABSTRACT

Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univer CM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univer CM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univer CM in managing system heterogeneity.

INDEX TERMS

Automata, Valves, Semantics, Computational modeling, Syntactics, Delay, Wires, multiprocessor, Formal specifications, modeling, simulation, electronic design automation

CITATION

Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Sara Vinco, "UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration",

*IEEE Transactions on Computers*, vol.62, no. 2, pp. 225-241, Feb. 2013, doi:10.1109/TC.2012.156REFERENCES

- [1] Accellera, “Verilog-AMS LRM,” URL: http://www.verilog.org/verilog-ams/htmlpages/ public-docs/lrm/2.3.1VAMS-LRM-2-3-1.pdf , 2012.
- [2] F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, and A. Sangiovanni-Vincentelli, “Metropolis: An Integrated Electronic System Design Environment,”
Computer, vol. 36, no. 4, pp. 45-52, Apr. 2003.- [3] K. Bertels, V.-M. Sima, Y. Yankova, G. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto, and A. Michelotti, “Hartes: Hardware-Software Codesign for Heterogeneous Multicore Platforms,”
IEEE Micro, vol. 30, no. 5, pp. 88 -97, Sept./Oct. 2010.- [4] F. Bouchhima, M. Briere, G. Nicolescu, M. Abid, and E. Aboulhamid, “A SystemC/Simulink Co-Simulation Framework for Continuous/Discrete-Events Simulation,”
Proc. IEEE Int'l Behavioral Modeling and Simulation Workshop (BMAS), pp. 1-6, 2007.- [5] C. Brandolese, W. Fornaciari, L. Pomante, F. Salice, and D. Sciuto, “Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC,”
IEEE Trans. Computers, vol. 55, no. 5, pp. 508-519, May 2006.- [6] D.D. Gajski, Z. Jianwen, R. Domer, A. Gerstlauer, and Z. Shuqing,
SpecC: Specification Language and Methodology. Springer, 2000.- [7] G. De Micheli, R. Ernst, and W. Wolf,
Readings in Hardware/Software Co-Design. Morgan Kaufmann Publishers, 2001.- [8] P. Diallo, J. Champeau, and V. Leilde, “Model Based Engineering for the Support of Models of Computation: The Cometa Approach,”
Proc. Int'l Workshop Multiparadigm Modeling (MPM), pp. 1-13, 2011.- [9] EDALab s.r.l., “HIFSuite,” URL: http:/www.hifsuite.com, 2012.
- [10] J. Eker, J.W. Janneck, E.A. Lee, J. Liu, X. Liu, J. Ludvig, S. Neuendorffer, S. Sachs, and Y. Xiong, “Taming Heterogeneity - The Ptolemy Approach,”
Proc. IEEE, vol. 91, no. 1, pp. 127-144, Jan. 2003.- [11] M. Fernandez,
Models of Computation - An Introduction to Computability Theory. Springer, 2009.- [12] G. Frehse, “PHAVer: Algorithmic Verification of Hybrid Systems Past HyTech,”
Proc. Hybrid Systems: Computation and Control, vol. 3414, pp. 258-273, 2005.- [13] F. Fummi, D. Quaglia, S. Vinco, G. Perbellini, and S. Saggin, “Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform,”
Proc. 10th Int'l Workshop Microprocessor Test and Verification (MTV), pp. 63-68, 2009.- [14] D.D. Gajski, N.D. Dutt, A.C.-H. Wuand, and S.Y.-L. Lin,
High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.- [15] L.D. Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, and S. Vinco, “univerCM: The UNIversal VERsatile Computational Model for Heterogeneous Embedded System Design,”
Proc. IEEE Int'l High Level Design Validation and Test Workshop (HLDVT), 2011.- [16] W. Haid, K. Huang, I. Bacivarov, and L. Thiele, “Multiprocessor SoC Software Design Flows,”
IEEE Signal Processing Magazine, vol. 26, no. 6, pp. 64-71, Nov. 2009.- [17] T. Henzinger, “The Theory of Hybrid Automata,”
Proc. IEEE 11th Ann. Symp. Logic in Computer Science (LICS), pp. 278-292, 1996.- [18] F. Herrera and E. Villar, “A Framework for Embedded System Specification under Different Models of Computation in SystemC,”
Proc. ACM/IEEE 43rd Design Automation Conf. (DAC), pp. 911-914, 2006.- [19] IEEE 1076.1 Working Group, “IEEE Standard VHDL Analog and Mixed-Signal Extensions,” 1999.
- [20] R. Kumar, D. Tullsen, N. Jouppi, and P. Ranganathan, “Heterogeneous Chip Multiprocessors,”
Computer, vol. 38, no. 11, pp. 32-38, Nov. 2005.- [21] E. Lee and A. Sangiovanni-Vincentelli, “Component-Based Design for the Future,”
Proc. ACM/IEEE Design Automation Test in Europe Conf. and Exhibition (DATE), pp. 1-5, 2011.- [22] T. MathWorks, “Stateflow: Design and Simulate State Machines and Control Logic,” URL: http://www.mathworks.com/ productsstateflow /, 2012.
- [23] Open SystemC Initiative, “SystemC,” URL: http:/www.systemc. org, 2012.
- [24] Open SystemC Initiative, “SystemC-AMS 1.0 Standard,” URL: http://www.systemc.org/downloads/standards ams10, 2012.
- [25] H. Patel, S. Shukla, and R. Bergamaschi, “Heterogeneous Behavioral Hierarchy Extensions for SystemC,”
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 765-780, Apr. 2007.- [26] J. Paul, D. Thomas, and A. Bobrek, “Scenario-Oriented Design for Single-Chip Heterogeneous Multiprocessors,”
IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 8, pp.868 -880, Aug. 2006.- [27] I. Sander and A. Jantsch, “System Modeling and Transformational Design Refinement in ForSyde,”
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 17-32, Jan. 2004.- [28] S. Shee and S. Parameswaran, “Design Methodology for Pipelined Heterogeneous Multiprocessor System,”
Proc. ACM/IEEE 44th Design Automation Conf. (DAC), pp. 811-816, 2007.- [29] C. Sonntag, R. Schiffelers, D. van Beek, J. Rooda, and S. Engell, “Modeling and Simulation Using the Compositional Interchange Format for Hybrid Systems,”
Proc. Sixth Int'l Conf. Math. Modeling (MATHMOD), pp. 640-650, 2009.- [30] The MathWorks, Inc. “Simulink 7.6,” http:/www.mathworks. com, 2010.
- [31] S. Tudoret, S. Nadjm-Tehrani, A. Beneviste, and J.-E. Strömberg, “Co-Simulation of Hybrid Systems: Signal-Simulink,”
Proc. Sixth Int'l Symp. Formal Techniques in Real-Time and Fault-Tolerant Systems (FTRTFT), pp. 134-151, 2000.- [32] M. Vasilevski, F. Pecheux, N. Beilleau, H. Aboushady, and K. Einwich, “Modeling Refining Heterogeneous Systems with SystemC-AMS: Application to WSN,”
Proc. ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 134-139, 2008.- [33] S. Vinco, D. Chatterjee, V. Bertacco, and F. Fummi, “SAGA: SystemC Acceleration on GPU Architectures,”
Proc. ACM/IEEE 49th Design Automation Conf. (DAC), 2012.- [34] H. Wong, A. Bracy, E. Schuchman, T.M. Aamodt, J.D. Collins, P.H. Wang, G. Chinya, A.K. Groen, H. Jiang, and H. Wang, “Pangaea: A Tightly-Coupled IA32 Heterogeneous Chip Multiprocessor,”
Proc. 17th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT), pp. 52-61, 2008.- [35] H.woo Park, H. Oh, and S. Ha, “Multiprocessor SoC Design Methods and Tools,”
IEEE Signal Processing Magazine, vol. 26, no. 6, pp. 72 -79, Nov. 2009. |