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Issue No.01 - Jan. (2013 vol.62)
pp: 31-44
Stanislavs Golubcovs , Newcastle University, Newcastle upon Tyne
Delong Shang , Newcastle University, Newcastle upon Tyne
Fei Xia , Newcastle University, Newcastle upon Tyne
Andrey Mokhov , Newcastle University, Newcastle upon Tyne
Alex Yakovlev , Newcastle University, Newcastle upon Tyne
This paper presents a novel type of asynchronous arbiter that allocates M interchangeable resources among N clients. This arbiter enables the concurrent utilization of multiple resources and is a useful device in various load-balancing circuits. Dedicated request signals from the resources and the clients are used in pairs to form each new grant. The 2\times 2 arbiter is examined as an accessible special case of the N\times M arbiter. A concurrent implementation is compared to fully sequential design. It is shown that the sequential design can be more practical when the time between a grant and the withdrawal of the initial request is small. The concurrent design provides higher performance in a system with a longer resource utilization time. A scalable tiled structure is developed to extend the arbiter structure beyond 2\times 2 to support N clients and M resources. Models and subsequent implementations of the tiles are presented. The tiles can be repeated without the use of additional connecting logic, enabling the construction of arbiters of larger sizes. Several examples demonstrate the usage of the arbiter.
Signal resolution, Logic gates, Integrated circuit modeling, Mathematical model, Concurrent computing, Equations, Availability, multiresource arbitration, Self-timed circuits, speed independent, asynchronous arbiters
Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov, Alex Yakovlev, "Concurrent Multiresource Arbiter: Design and Applications", IEEE Transactions on Computers, vol.62, no. 1, pp. 31-44, Jan. 2013, doi:10.1109/TC.2011.218
[1] D. Lattard, E. Beigne, F. Clermidy, Y. Durand, R. Lemaire, P. Vivet, and F. Berens, “A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 223-235, Jan. 2008.
[2] A. Lines, “Asynchronous Interconnect for Synchronous SoC Design,” IEEE Micro, vol. 24, no. 1, pp. 32-41, Jan. 2004.
[3] C.E. Leiserson, “Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing,” IEEE Trans. Computer, vol. 34, no. 10, pp. 892-901, Oct. 1985.
[4] Y. Tamir and H.-C. Chi, “Symmetric Crossbar Arbiters for VlSI Communication Switches,” IEEE Trans. Parallel and Distributed Systems, vol. 4, no. 1, pp. 13-27, Jan. 1993.
[5] T. Mudge, J. Hayes, and D. Winsor, “Multiple Bus Architectures,” Computer, vol. 20, no. 6, pp. 42-48, June 1987.
[6] D.J. Kinniment, Synchronization and Arbitration in Digital Systems. John Wiley & Sons, Ltd, 2007.
[7] K.M. Chandy, Parallel Program Design: A Foundation. Addison-Wesley Longman Publishing Co., Inc., 1988.
[8] I. Benko and J. Ebergen, “Delay-Insensitive Solutions to the Committee Problem,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 228-237, Nov. 1994.
[9] “Petrify tool,” html , 2011.
[10] J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces. Springer-Verlag, 2002.
[11] J. Sparsø, “Asynchronous Circuit Design—A Tutorial,” Principles of Asynchronous Circuit Design - A Systems Perspective, chapters 1-8, pp. 1-152, Kluwer Academic Publishers, Dec. 2001.
[12] K.V. Berkel and C. Molnar, “Beware the Three-Way Arbiter,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 840-848, June 1999.
[13] D.E. Muller and W.S. Bartky, “A Theory of Asynchronous Circuits,” Proc. Int'l Symp. Theory of Switching, pp. 204-243, 1959.
[14] R.C. Pearce, J.A. Field, and W.D. Little, “Asynchronous Arbiter Module,” IEEE Trans. Computers, vol. 24, no. 9, pp. 931-932, Sept. 1975.
[15] C.L. Seitz, “Ideas about Arbiters,” Lambda, vol. 1, pp. 10-14, 1980.
[16] “Punf:” toolspunf/, 2011.
[17] V. Khomenko, “Model Checking Based on Prefixes of Petri Net Unfoldings,” PhD dissertation, Univ. of Newcastle upon Tyne, Feb. 2003.
[18] I. Poliakov, V. Khomenko, and A. Yakovlev, “Workcraft—A Framework for Interpreted Graph Models,” PETRI NETS '09: Proc. 30th Int'l Conf. Applications and Theory of Petri Nets, pp. 333-342, 2009.
[19] D. Shang, F. Xia, S. Golubcovs, and A. Yakovlev, “The Magic Rule of Tiles: Virtual Delay Insensitivity,” Proc. Int'l Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 286-296, 2009.
[20] A. Bystrov, D.J. Kinniment, and A. Yakovlev, “Priority Arbiters,” ASYNC '00: Proc. Sixth Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 128-137, 2000.
[21] A. Yakovlev, “Designing Arbiters Using Petri Nets,” Proc. Israel Workshop Asynchronous Very Large Scale Integration (VLSI), pp. 179-201, 1995.
[22] A. Winstanley, A. Garivier, and M. Greenstreet, “An Event Spacing Experiment,” Proc. Eighth Int'l Symp. Asynchronous Circuits and Systems, pp. 47-56, Apr. 2002.
[23] S.S. Patil, “Forward Acting n x m Arbiter,” technical report, Computation Structures Group Memo 67, MIT, 1972.
[24] C. van Berkel and T. van Roermund, “Scalable Multi-Input-Multi-Output Queues with Application to Variation-Tolerant Architectures,” IEEE Trans. Very Large Scale Integration Systems, vol. 17, no. 7, pp. 920-923, July 2009.
[25] J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design. Kluwer Academic Publishers, 2002.
[26] W. Song and D. Edwards, “Improving the Throughput of Asynchronous on-Chip Networks with Sdm,” Proc. United Kingdom Electronics Forum, June 2010.
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