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Optimizing Hardware Design by Composing Utility-Directed Transformations
Dec. 2012 (vol. 61 no. 12)
pp. 1800-1812
Qiang Liu, Imperial College London, London
Tim Todman, Imperial College London, London
Wayne Luk, Imperial College London, London
George A. Constantinides, Imperial College London, London
Utility-directed transformations involve changing a design to optimize for given constraints while preserving behavior. These changes are often achieved by techniques such as linear programming or geometric programming. We present a systematic approach composing multiple utility-directed transformations for optimizing and mapping a sequential design onto a customizable parallel computing platform such as a Field-Programmable Gate Array (FPGA). Our aim is to enable automatic design optimization at compile time. Design goals specified by users drive the design transformations. Each utility-directed transformation achieves part of the overall goal, and multiple utility-directed transformations, connected by pattern-directed transformations, are composed to fulfill the overall design requirements. The utility-directed transformations in this work produce performance-optimized designs by exploiting data reuse, MapReduce, and pipelining for the target parallel computing platform. Moreover, it is shown that performing transformations in different orders allows users to trade speed for resources, and design performance for compile time. Several applications are used to evaluate this approach on FPGAs. The system performance of a 64-bit matrix multiplication is shown to improve up to 98 times compared to the original design, in the target hardware platform.
Index Terms:
Energy efficiency,Pipeline processing,Energy management,Electricity supply industry,Design optimization,Optimization,Geometric programming,geometric programming,Design optimization,data reuse,MapReduce,pipelining
Citation:
Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides, "Optimizing Hardware Design by Composing Utility-Directed Transformations," IEEE Transactions on Computers, vol. 61, no. 12, pp. 1800-1812, Dec. 2012, doi:10.1109/TC.2011.205
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