The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.10 - Oct. (2012 vol.61)
pp: 1484-1494
Vinay Hanumaiah , Arizona State University, Tempe
Sarma Vrudhula , Arizona State University, Tempe
ABSTRACT
This paper addresses the problem of determining the feasible speeds and voltages of multicore processors with hard real-time and temperature constraints. This is an important problem, which has applications in time-critical execution of programs like audio and video encoding on application-specific embedded processors. Two problems are solved. The first is the computation of the optimal time-varying voltages and speeds of each core in a heterogeneous multicore processor, that minimize the makespan—the latest completion time of all tasks, while satisfying timing and temperature constraints. The solution to the makespan minimization problem is then extended to the problem of determining the feasible speeds and voltages that satisfy task deadlines. The methods presented in this paper also provide a theoretical basis and analytical relations between speed, voltage, power and temperature, which provide greater insight into the early-phase design of processors and are also useful for online dynamic thermal management.
INDEX TERMS
Multicore processing, Program processors, Temperature dependence, Equations, Voltage control, Minimization, Optimization, optimal control., Multicore, performance optimization, real-time, task deadlines, dynamic voltage and frequency scaling, thermal management, makespan minimization, leakage dependence on temperature
CITATION
Vinay Hanumaiah, Sarma Vrudhula, "Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors", IEEE Transactions on Computers, vol.61, no. 10, pp. 1484-1494, Oct. 2012, doi:10.1109/TC.2011.156
REFERENCES
[1] S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro, vol. 19, no. 4, pp. 23-29, July/Aug. 1999.
[2] W. Huang, M.R. Stan, K. Skadron, K. Sankaranarayanan, and S. Ghosh, "HotSpot: A Compact Thermal Modeling Method for CMOS VLSI Systems," IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 5, pp. 501-513, May 2006.
[3] W. Liao, L. He, and K.M. Lepak, "Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 1042-1053, July 2005.
[4] S. Zhang and K.S. Chatha, "Approximation Algorithm for the Temperature-Aware Scheduling Problem," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '07), pp. 281-288, 2007.
[5] A. Cohen, F. Finkelstein, A. Mendelson, R. Ronen, and D. Rudoy, "On Estimating Optimal Performance of CPU Dynamic Thermal Management," IEEE Computer Architecture Letters, vol. 2, no. 1, p. 6, Jan. 2003.
[6] K. Skadron, M.R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan, "Temperature-Aware Microarchitecture: Modeling and Implementation," ACM Trans. Architecture and Code Optimization, vol. 1, pp. 94-125, 2004.
[7] D. Brooks and M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors," Proc. Seventh Int'l Symp. High-Performance Computer Architecture (HPCA '01), pp. 171-182, 2001.
[8] G. Quan, Y. Zhang, W. Wiles, and P. Pei, "Guaranteed Scheduling for Repetitive Hard Real-Time Tasks Under the Maximal Temperature Constraint," Proc. Sixth IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '08), pp. 267-272, 2008.
[9] R. Rao and S. Vrudhula, "Performance Optimal Processor Throttling under Thermal Constraints," Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems (CASES '07), pp. 257-266, 2007.
[10] R. Jayaseelan and T. Mitra, "Temperature Aware Task Sequencing and Voltage Scaling," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '08), pp. 618-623, 2008.
[11] S. Wang and R. Bettati, "Reactive Speed Control in Temperature-Constrained Real-Time Systems," Proc. 18th Euromicro Conf. Real-Time Systems (ECRTS), pp. 161-170, 2006.
[12] T. Chantem, X.S. Hu, and R.P. Dick, "Online Work Maximization under a Peak Temperature Constraint," Proc. 14th ACM/IEEE Int'l Symp. Low Power Electronics and Design (ISLPED '09), pp. 105-110, 2009.
[13] S. Cho and R. Melhem, "Corollaries to Amdahl's Law for Energy," IEEE Computer Architecture Letters, vol. 7, no. 1, pp. 25-28, Jan. 2008.
[14] J. Li and J.F. Martínez, "Power-performance Considerations of Parallel Computing on Chip Multiprocessors," ACM Trans. Architecture and Code Optimization, vol. 2, pp. 397-422, 2005.
[15] R. Rao and S. Vrudhula, "Fast and Accurate Prediction of the Steady State Throughput of Multi-Core Processors under Thermal Constraints," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1559-1572, Oct. 2009.
[16] P. Chaparro, J. González, G. Magklis, Q. Cai, and A. González, "Understanding the Thermal Implications of Multicore Architectures," IEEE Trans. Parallel and Distributed Systems, vol. 18, no. 8, pp. 1055-1065, Aug. 2007.
[17] S. Heo, K. Barr, and K. Asanovic, "Reducing Power Density through Activity Migration," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '03), pp. 217-222, 2003.
[18] N. Bansal, T. Kimbrel, and K. Pruhs, "Speed Scaling to Manage Energy and Temperature," J. ACM, vol. 54, pp. 3:1-3:39, Mar. 2007.
[19] S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, and G.D. Micheli, "Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization," Proc. Fifth IEEE/ACM Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '08), pp. 111-116, 2008.
[20] R. Mukherjee and S.O. Memik, "Physical Aware Frequency Selection for Dynamic Thermal Management in Multi-Core Systems," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '06), pp. 547-552, 2006.
[21] R. Rao and S. Vrudhula, "Efficient Online Computation of Core Speeds to Maximize the Throughput of Thermally Constrained Multi-Core Processors," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '08), pp. 537-542, 2008.
[22] V. Hanumaiah, S. Vrudhula, and K.S. Chatha, "Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints," Proc. Conf. Design, Automation and Test in Europe (DATE '09), pp. 288-293, 2009.
[23] V. Hanumaiah, S. Vrudhula, and K.S. Chatha, "Maximizing Performance of Thermally Constrained Multi-Core Processors by Dynamic Voltage and Frequency Control," Proc. Int'l Conf. Computer-Aided Design (ICCAD), pp. 310-313, 2009.
[24] K. Stavrou and P. Trancoso, "Thermal-Aware Scheduling for Future Chip Multiprocessors," EURASIP J. Embedded Systems, vol. 2007, p. 40, 2007.
[25] A. Coskun, T. Rosing, and K. Gross, "Proactive Temperature Balancing for Low Cost Thermal Management in MPSoCs," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 250-257, 2008.
[26] A. Coskun, T. Rosing, K. Whisnant, and K. Gross, "Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 9, pp. 1127-1140, Sept. 2008.
[27] M.D. Powell, M. Gomaa, and T.N. Vijaykumar, "Heat-and-Run: Leveraging SMT and CMP to Manage Power Density through the Operating System," Proc. 11th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 260-270, 2004.
[28] F. Mulas, M. Pittau, M. Buttu, S. Carta, A. Acquaviva, L. Benini, and D. Atienza, "Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures," Proc. Conf. Design, Automation and Test in Europe (DATE '08), pp. 734-739, 2008.
[29] T. Chantem, R.P. Dick, and X.S. Hu, "Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs," Proc. Conf. Design, Automation and Test in Europe (DATE '08), pp. 288-293, 2008.
[30] Y. Wang, K. Ma, and X. Wang, "Temperature-Constrained Power Control for Chip Multiprocessors with Online Model Estimation," ACM SIGARCH Computer Architecture News, vol. 37, pp. 314-324, 2009.
[31] J. Donald and M. Martonosi, "Techniques for Multicore Thermal Management: Classification and New Exploration," ACM SIGARCH Computer Architecture News, vol. 34, no. 2, pp. 78-88, 2006.
[32] P. Michaud, A. Seznec, D. Fetis, Y. Sazeides, and T. Constantinou, "A Study of Thread Migration in Temperature-Constrained Multicores," ACM Trans. Architecture and Code Optimization, vol. 4, pp. 9-1-9-28, 2007.
[33] T. Constantinou, Y. Sazeides, P. Michaud, D. Fetis, and A. Seznec, "Performance Implications of Single Thread Migration on a Chip Multi-Core," ACM SIGARCH Comp. Architecture News—Special Issue (dasCMP '05), vol. 33, pp. 80-91, 2005.
[34] S. Borkar, "Thousand Core Chips—A Technology Perspective," Proc. Design Automation Conf. (DAC '07), pp. 746-749, 2007.
[35] M. Hill and M. Marty, "Amdahl's Law in the Multicore Era," Computer, vol. 41, no. 7, pp. 33-38, July 2008.
[36] NVIDIA Compute Unified Device Architecture: Programming Guide, June 2008.
[37] R. Rao, S. Vrudhula, and K. Berezowski, "Analytical Results for Design Space Exploration of Multi-Core Processors Employing Thread Migration," Proc. 13th Int'l Symp. Low Power Electronics and Design (ISLPED '08), pp. 229-232, 2008.
[38] Second Generation Intel® Core$^{\rm TM}$ Processor Family Desktop and Intel® Pentium$^{\rm TM}$ Processor Family Desktop, and LGA1155 Socket, Intel Corp., May 2011.
[39] R. Rao, S. Vrudhula, and C. Chakrabarti, "Throughput of Multi-Core Processors under Thermal Constraints," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '07), pp. 201-206, 2007.
[40] D.E. Kirk, Optimal Control Theory, Prentice-Hall, 1970.
[41] R.F. Hartl, S.P. Sethi, and R.G. Vickson, "A Survey of the Maximum Principles for Optimal Control Problems with State Constraints," SIAM Rev., vol. 37, pp. 181-218, 1995.
[42] M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown, "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," Proc. IEEE Int'l Workshop Workload Characterization (WWC), pp. 3-14, 2001.
35 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool