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Issue No.08 - Aug. (2012 vol.61)
pp: 1179-1188
Irith Pomeranz , Purdue University, West Lafayette
Multicycle (multipattern) scan-based tests contain multiple clock cycles between scan operations. Each such clock cycle defines a pattern of the test. Multipattern tests require fewer clock cycles for test application compared with single-pattern or two-pattern tests for the same target faults. In addition, this paper demonstrates that patterns appearing later in a test typically have lower switching activity than patterns appearing earlier in the test. Based on these observations, the paper presents a static test compaction procedure for multipattern tests that targets a reduction in switching activity while reducing the number of clock cycles required for test application. The procedure is based on an operation called test merging. Merging of a test pair causes the patterns from both tests to appear in a single test. By placing the patterns from a test with a high switching activity at the end of a merged test, their switching activity can be reduced. The proposed procedure combines the test merging procedure with a procedure that modifies a test set so as to reduce its switching activity. Through this procedure it takes advantage of the opportunities created by test merging to reduce the switching activity of patterns that appear later in a test.
Multicycle tests, static test compaction, switching activity, transition faults.
Irith Pomeranz, "On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests", IEEE Transactions on Computers, vol.61, no. 8, pp. 1179-1188, Aug. 2012, doi:10.1109/TC.2011.184
[1] S.Y. Lee and K.K. Saluja, "Test Application Time Reduction for Sequential Circuits with Scan," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 9, pp. 1128-1140, Sept. 1995.
[2] I. Pomeranz and S.M. Reddy, "Static Test Compaction for Scan-Based Designs to Reduce Test Application Time," Proc. Seventh Asian Test Symp., pp. 198-203, 1998.
[3] I. Pomeranz and S.M. Reddy, "Forming Multi-Cycle Tests for Delay Faults by Concatenating Broadside Tests," Proc. VLSI Test Symp., 2010.
[4] I. Pomeranz, "Generation of Multi-Cycle Broadside Tests," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 8, pp. 1253-1257, Aug. 2011.
[5] P.C. Maxwell, R.C. Aitken, K.R. Kollitz, and A.C. Brown, "IDDQ and AC Scan: The War Against Unmodelled Defects," Proc. Int'l Test Conf., pp. 250-258, 1996.
[6] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S.M. Reddy, "Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1325-1333, Dec. 1998.
[7] S. Gerstendorfer and H.J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST," Proc. Int'l Test Conf., pp. 77-84, 1999.
[8] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, "Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption," Proc. Eight Asian Test Symp., pp. 89-94, 1999.
[9] R. Sankaralingam, R.R. Oruganti, and N.A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," Proc. VLSI Test Symp., pp. 35-40, 2000.
[10] L. Whetsel, "Adapting Scan Architectures for Low Power Operation," Proc. Int'l Test Conf., pp. 863-872, 2000.
[11] K.-J. Lee, T.-C. Huang, and J.-J. Chen, "Peak-Power Reduction for Multiple-Scan Circuits During Test Application," Proc. Ninth Asian Test Symp., pp. 453-458, 2000.
[12] J. Saxena, K.M. Butler, and L. Whetsel, "An Analysis of Power Reduction Techniques in Scan Testing," Proc. Int'l Test Conf., pp. 670-677, 2001.
[13] P.M. Rosinger, B.M. Al-Hashimi, and N. Nicolici, "Scan Architecture for Shift and Capture Cycle Power Reduction," Proc. Defect and Fault Tolerance Symp., pp. 129-137, 2002.
[14] S. Kajihara, K. Ishida, and K. Miyase, "Test Vector Modification for Power Reduction during Scan Testing," Proc. VLSI Test Symp., pp. 160-165, 2002.
[15] A. Chandra and K. Chakrabarty, "Reduction of SOC Test Data Volume, Scan Power and Testing Time Using Alternating Run-Length Codes," Proc. 39th Design Automation Conf., pp. 673-678, 2002.
[16] D. Xiang, S. Gu, J.-G. Sun, and Y.-L. Wu, "A Cost-Effective Scan Architecture for Scan Testing with Nonscan Test Power and Test Application Cost," Proc. Design Autom Conf., pp. 744-747, 2003.
[17] J. Saxena, K.M. Butler, V.B. Jayaram, S. Kundu, N.V. Arvind, P. Sreeprakash, and M. Hachinger, "A Case Study of IR-Drop in Structured At-Speed Testing," Proc. Int'l Test Conf., pp. 1098-1104, 2003.
[18] W. Li, S.M. Reddy, and I. Pomeranz, "On Test Generation for Transition Faults with Minimized Peak Power Dissipation," Proc. 41st Design Automation Conf., pp. 504-509, 2004.
[19] K.M. Butler, J. Saxena, A. Jain, T. Fryars, J. Lewis, and G. Hetherington, "Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques," Proc. Int'l Test Conf., pp. 355-364, 2004.
[20] K. Lee, S. Hsu, and C. Ho, "Test Power Reduction with Multiple Capture Orders," Proc. Asian Test Symp., pp. 26-31, 2004.
[21] W. Li, S.M. Reddy, and I. Pomeranz, "On Reducing Peak Current and Power During Test," Proc. IEEE CS Ann. Symp. Very-Large-Scale Integration, pp. 156-161, 2005.
[22] X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K.K. Saluja, and K. Kinoshita, "Low-Capture-Power Test Generation for Scan-Based Testing," Proc. Int'l Test Conf., pp. 1019-1028, 2005.
[23] V.R. Devanathan, C.P. Ravikumar, and V. Kamakoti, "On Power-Profiling and Pattern Generation for Power-Safe Scan Tests," Proc. Design, Automation and Test in Europe Conf., pp. 1-6, 2007.
[24] J. Lee, S. Narayan, M. Kapralos, and M. Tehranipoor, "Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation," Proc. Design, Automation and Test in Europe Conf., pp. 1172-1177, 2008.
[25] J. Lee and M. Tehranipoor, "LS-TDF: Low-Switching Transition Delay Fault Pattern Generation," Proc. VLSI Test Symp., pp. 227-232, 2008.
[26] X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K.K. Saluja, "A Capture-Safe Test Generation Scheme for At-Speed Scan Testing," Proc. European Test Symp., pp. 55-60, 2008.
[27] I. Pomeranz and S.M. Reddy, "Functional Broadside Tests with Minimum and Maximum Switching Activity," ASP J. Low Power Electronics, vol. 4, pp. 429-437, Dec. 2008.
[28] C.-W. Tzeng and S.-Y. Huang, "QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 11, pp. 1756-1766, Nov. 2009.
[29] A. Sabne, R. Tiwari, A. Shrivastava, S. Ravi, and R. Parekhji, "A Generic Low Power Scan Chain Wrapper for Designs Using Scan Compression," Proc. VLSI Test Symp., pp. 135-140, 2010.
[30] M.-F. Wu, H.-C. Pan, T.-H. Wang, J.-L. Huang, K.-H. Tsai, and W.-T. Cheng, "Improved Weight Assignment for Logic Switching Activity during At-Speed Test Pattern Generation," Proc. Asia and South Pacific Design Automation Conf., pp. 493-498, 2010.
[31] J. Rearick, "Too Much Delay Fault Coverage is a Bad Thing," Proc. Int'l Test Conf., pp. 624-633, 2001.
[32] I. Pomeranz, "On the Generation of Scan-Based Test Sets with Reachable States for Testing under Functional Operation Conditions," Proc. 41st Ann. Design Automation Conf., pp. 928-933, 2004.
[33] I. Pomeranz and S.M. Reddy, "Definition and Generation of Partially-Functional Broadside Tests," IET Computers and Digital Techniques, vol. 3, pp. 1-13, Jan. 2009.
[34] K.-T. Cheng, "Transition Fault Testing for Sequential Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1971-1983, Dec. 1993.
[35] I. Pomeranz and S.M. Reddy, "On-Chip Generation of the Second Primary Input Vectors of Broadside Tests," Proc. IEEE 24th Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 38-46, 2009.
[36] C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, "OPMISR: The Foundation for Compressed ATPG Vectors," Proc. Int'l Test Conf., pp. 748-757, 2001.
[37] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.-H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide, and J. Qian, "Embedded Deterministic Test for Low Cost Manufacturing Test," Proc. Int'l Test Conf., pp. 301-310, 2002.
[38] I. Pomeranz and S.M. Reddy, "Forward-Looking Fault Simulation for Improved Static Compaction," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 10, pp. 1262-1265, Oct. 2001.
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