
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Mehran MozaffariKermani, Arash ReyhaniMasoleh, "Efficient and HighPerformance Parallel Hardware Architectures for the AESGCM," IEEE Transactions on Computers, vol. 61, no. 8, pp. 11651178, Aug., 2012.  
BibTex  x  
@article{ 10.1109/TC.2011.125, author = {Mehran MozaffariKermani and Arash ReyhaniMasoleh}, title = {Efficient and HighPerformance Parallel Hardware Architectures for the AESGCM}, journal ={IEEE Transactions on Computers}, volume = {61}, number = {8}, issn = {00189340}, year = {2012}, pages = {11651178}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.125}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Efficient and HighPerformance Parallel Hardware Architectures for the AESGCM IS  8 SN  00189340 SP1165 EP1178 EPD  11651178 A1  Mehran MozaffariKermani, A1  Arash ReyhaniMasoleh, PY  2012 KW  Advanced encryption standard KW  Galois/Counter mode KW  high performance KW  low power. VL  61 JA  IEEE Transactions on Computers ER   
[1] Nat'l Inst. of Standards and Tech nologies "Announcing the Advanced Encryption Standard (AES)," Fed. Information Processing Standards Publication, no. 197, Nov. 2001.
[2] WiFi, http://standards.ieee.org/getieee802/download 802. 112007.pdf, 2011.
[3] WiMAX, http://standards.ieee.org/getieee802/download 802.16e2005.pdf, 2011.
[4] S. Trimberger, "Security in SRAM FPGAs," IEEE Design and Test of Computers, vol. 24, no. 6, p. 581, Nov./Dec. 2007.
[5] M. Dworkin, "Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC," NIST SP, 80038D, 2007.
[6] IEEE Standard for Local and Metropolitan Area Networks, Media Access Control (MAC) Security, 2006.
[7] Fibre Channel Security Protocols (FCSP), http://www.t10.org/ftp/t11/document.0606157v0.pdf . 2006.
[8] Algotronics Ltd.: GCM Extension for AES G3 Core, 2007.
[9] Helion Technology: AESGCM Cores, 2007.
[10] Elliptic Semiconductor Inc.: CLP15: UltraHigh Throughput AESGCM Core40 Gbps, 2008.
[11] E. Käsper and P. Schwabe, "Faster and TimingAttack Resistant AESGCM," Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES '09), pp. 117, 2009.
[12] K. Jankowski and P. Laurent, "Packed AESGCM Algorithm Suitable for AES/PCLMULQDQ Instructions," IEEE Trans. Computers, vol. 60, no. 1, pp. 135138, Jan. 2011.
[13] S. Morioka and A. Satoh, "An Optimized SBox Circuit Architecture for Low Power AES Design," Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES '02), pp. 172186, Aug. 2002.
[14] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, "A Compact Rijndael Hardware Architecture with SBox Optimization," Proc. Int'l Conf. Theory and Application of Cryptology and Information Security: Advances in Cryptology (ASIACRYPT '01), pp. 239254, Dec. 2001.
[15] J. Wolkerstorfer, E. Oswald, and M. Lamberger, "An ASIC Implementation of the AES SBoxes," Proc. Cryptographers Track at the RSA Conf. (CTRSA '02), pp. 6778, Jan. 2002.
[16] X. Zhang and K.K. Parhi, "HighSpeed VLSI Architectures for the AES Algorithm," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 957967, Sept. 2004.
[17] T. Good and M. Benaissa, "692nW Advanced Encryption Standard (AES) on a $0.13\mu {\rm m}$ CMOS," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 12, pp. 17531757, Dec. 2010.
[18] M. MozaffariKermani and A. ReyhaniMasoleh, "A LowCost Sbox for the Advanced Encryption Standard Using Normal Basis," Proc. IEEE Int'l Conf. Electro/Information Technology (EIT '09), pp. 5255, 2009.
[19] S. Tillich, M. Feldhofer, T. Popp, and J. Großschädl, "Area, Delay, and Power Characteristics of StandardCell Implementations of the AES SBox," J. Signal Processing Systems, vol. 50, pp. 251261, 2008.
[20] D. Canright, "A Very Compact SBox for AES," Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES '05), pp. 441455, Sept. 2005.
[21] N. Mentens, L. Batina, B. Preneel, and I. Verbauwhede, "A Systematic Evaluation of Compact Hardware Implementations for the Rijndael SBox," Proc. Cryptographers Track at the RSA Conf. (CTRSA '05), pp. 323333, 2005.
[22] X. Zhang and K.K. Parhi, "On the Optimum Constructions of Composite Field for the AES Algorithm," IEEE Trans. Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 11531157, Oct. 2006.
[23] J. Boyar and R. Peralta, "A New Combinational Logic Minimization Technique with Applications to Cryptology," Proc. Int'l Symp. Experimental Algorithms (SEA '10), pp. 178189, 2010.
[24] S. Nikova, V. Rijmen, and M. Schläffer, "Using Normal Bases for Compact Hardware Implementations of the AES SBox," Proc. Int'l Conf. Security and Cryptography for Networks (SCN '08), pp. 236245, 2008.
[25] Y. Nogami, K. Nekado, T. Toyota, N. Hongo, and Y. Morikawa, "Mixed Bases for Efficienct Inversion in ${F}_{((2^2)^2)^2}$ and Conversion Matrices of SubBytes of AES," Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES '10), pp. 234247, Aug. 2010.
[26] D. Canright and D.A. Osvik, "A More Compact AES," Selected Areas in Cryptography, pp. 157169, SpringerVerlag, 2009.
[27] S. Lemsitzer, J. Wolkerstorfer, N. Felbert, and M. Braendli, "MultiGigabit GCMAES Architecture Optimized for FPGAs," Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES '07), pp. 227238, 2007.
[28] P. Patel, "Parallel Multiplier Designs for the Galois/Counter Mode of Operation," Master of Applied Science thesis, The Univ. of Waterloo, 2008.
[29] B. Yang, S. Mishra, and R. Karri, "High Speed Architecture for Galois/Counter Mode of Operation (GCM)," Cryptology ePrint Archive: Report 2005/146 June 2005.
[30] D.A. McGrew and J. Viega, "The Galois/Counter Mode of Operation (GCM)," NIST Modes Operation Symmetric Key Block Ciphers, http://csrc.nist.gov/groups/ST/toolkit/BCM/ documents/proposedmodes/gcmgcmrevisedspec.pdf , 2005.
[31] A. Satoh, "HighSpeed Parallel Hardware Architecture for Galois Counter Mode," Proc. Int'l Symp. Circuits and Systems (ISCAS), pp. 18631866, 2007.
[32] A. Satoh, T. Sugawara, and T. Aoki, "HighPerformance Hardware Architectures for Galois Counter Mode," IEEE Trans. Computers, vol. 58, no. 7, pp. 917930, July 2009.
[33] N. Meloni, C. Nègre, and M.A. Hasan, "High Performance GHASH Function for Long Messages," Proc. Int'l Conf. Applied Cryptography and Network Security (ACNS '10), pp. 154167, 2010.
[34] Synopsys, http:/www.synopsys.com/, 2011.
[35] STMicroelectronics, http:/www.st.com/, 2011.
[36] ModelSim, http:/www.model.com/, 2011.
[37] M. McLoone and J.V. McCanny, "High Performance SingleChip FPGA Rijndael Algorithm Implementations," Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES '01), pp. 6576, 2001.
[38] F.X. Standaert, G. Rouvroy, J.J. Quisquater, and J.D. Legat, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs," Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES '03), pp. 334350, Sept. 2003.
[39] P. Bulens, F.X. Standaert, J.J. Quisquater, P. Pellegrin, and G. Rouvroy, "Implementation of the AES128 on Virtex5 FPGAs," Proc. Cryptology in Africa First Int'l Conf. Progress in Cryptology (AFRICACRYPT '08), pp. 1626, 2008.
[40] A. Hodjat and I. Verbauwhede, "AreaThroughput TradeOffs for Fully Pipelined 30 to 70 Gbits/s AES Processors," IEEE Trans. Computers, vol. 55, no. 4, pp. 366372, Apr. 2006.
[41] Mathworks, http:/www.mathworks.com/, 2011.
[42] S.Y. Lin and C.T. Huang, "A HighThroughput LowPower AES Cipher for Network Applications," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '07), pp. 595600, 2007.
[43] D.E. Knuth, The Art of Computer Programming: SemiNumerical Algorithms, vol. 2, pp. 441466. AddisonWesley, 1981.
[44] R. Lidl and H. Niederreiter, Introduction to Finite Fields and Their Applications. Cambridge Univ. Press, 1994.
[45] O. Gustafsson and M. Olofsson, "Complexity Reduction of Constant Matrix Computations over the Binary Field," Proc. Int'l Workshop Arithmetic of Finite Fields (WAIFI '07), pp. 103115, 2007.
[46] H. Yi, J. Song, S. Park, and C. Park, "Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems," Proc. Int'l Conf. Comm. Systems (ICCS '06), pp. 15, 2006.
[47] G. Zhou, H. Michalik, and L. Hinsenkamp, "Improving Throughput of AESGCM with Pipelined Karatsuba Multipliers on FPGAs," Proc. Int'l Workshop Reconfigurable Computing: Architectures, Tools and Applications (ARC '09), pp. 193203, 2009.
[48] J. Lázaro, A. Astarloa, U. Bidarte, J. Jiménez, and A. Zuloaga, "AESGalois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications," Proc. Int'l Workshop Reconfigurable Computing: Architectures, Tools and Applications (ARC '09), pp. 312317, 2009.
[49] E.D. Mastrovito, "VLSI Architectures for Computation in Galois Fields," PhD thesis, Linköping Univ., 1991.
[50] A. Karatsuba and Y. Ofman, "Multiplication of Multidigit Numbers on Automata," Soviet Physics Doklady, vol. 7, pp. 595596, 1963.
[51] H. Fan and M.A. Hasan, "A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields," IEEE Trans. Computers, vol. 56, no. 2, pp. 224233, Feb. 2007.
[52] A. ReyhaniMasoleh and M.A. Hasan, "Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over $GF({2^{m}})$ ," IEEE Trans. Computers, vol. 53, no. 8, pp. 945959, Aug. 2004.
[53] G. Zhou, H. Michalik, and L. Hinsenkamp, "Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on KaratsubaOfman Algorithm on FPGAs," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, pp. 10571066, July 2010.