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Issue No.08 - Aug. (2012 vol.61)

pp: 1059-1070

Wei Liu , Politecnico di Torino, Torino

Alberto Nannarelli , Technical University of Denmark, Lyngby

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.82

ABSTRACT

Although division and square root are not frequent operations, most processors implement them in hardware to not compromise the overall performance. Two classes of algorithms implement division or square root: digit-recurrence and multiplicative (e.g., Newton-Raphson) algorithms. Previous work shows that division and square root units based on the digit-recurrence algorithm offer the best tradeoff delay-area-power. Moreover, the two operations can be combined in a single unit. Here, we present a radix-16 combined division and square root unit obtained by overlapping two radix-4 stages. The proposed unit is compared to similar solutions based on the digit-recurrence algorithm and it is compared to a unit based on the multiplicative Newton-Raphson algorithm.

INDEX TERMS

Floating point, division, square root, digit-recurrence.

CITATION

Wei Liu, Alberto Nannarelli, "Power Efficient Division and Square Root Unit",

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