E. Antelo is with the Departamento de Electrónica e Computación, Universidade de Santiago de Campostela, 15706 Santiago de Compostela, Spain. E-mail: email@example.com.
D. Hough is with Oracle Corporation, 4180 Network Circle, Santa Clara, CA 95054. E-mail: firstname.lastname@example.org.
P. Ienne is with École Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, 1015 Lausanne, CH-Switzerland. E-mail: email@example.com.
For information on obtaining reprints of this paper, please send e-mail to: firstname.lastname@example.org.
Elisardo Antelo graduated with a degree in physics in 1991 and received the PhD in computer engineering in 1995 from the University of Santiago de Compostela, Spain. In 1992, he joined the Departamento de Electronica e Computacion at the University of Santiago de Compostela. From 1992 to 1998, he was an assistant professor and since 1998 he has been a tenured associate professor in this department. He was a research visitor at the University of California at Irvine several times between 1996 and 2000. Dr. Antelo is a member of the Computer Architecture group at the University of Santiago de Compostela. Since 2001, he has been involved in the program committee of the IEEE Symposium on Computer Arithmetic (program cochair in the 2011 edition). He also was involved with the program committees of the Real Numbers and Computers Conference since 2006 and EUROSIPCO since 2008. He is associate editor of the IEEE Transactions on Computers (since 2007), and of Integration, the VLSI Journal (since 2011). His primary research and teaching interest are in digital design and computer architecture with current emphasis on high-speed and low-power numerical processors, application-specific modules, computer arithmetic and design issues related to multicore processors.
David Hough is a graduate of Carleton College, with a BA in astronomy in 1968. He received the PhD in computer science in 1977 from the University of California. After working at Tektronix and Apple Computer, he joined Sun Microsystems in 1984, as a distinguished engineer since 1989. In 2010, Sun became part of Oracle Corporation, where he is now a senior principal software engineer, working in the areas of software and hardware support for numerical computation. In 1978, he became active in the P754 standardization effort for microprocessor arithmetic, which resulted in the ANSI/IEEE 754-1985 Standard for Binary Floating-Point Arithmetic and the ANSI/IEEE 854-1987 Standard for Radix-Independent Floating-Point Arithmetic. Likewise, beginning in 2000, he served in the effort to produce the revised ANSI/IEEE 754-2008 Standard for Floating-Point Arithmetic. He has served on the program committees for the IEEE Symposia on Computer Arithmetic since 1998. He is a member of the IEEE and the IEEE Computer Society.
Paolo Ienne has been a professor at the École Polytechnique Fédérale de Lausanne (EPFL) since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, from 1990 to 1991, he was an undergraduate researcher with Brunel University, Uxbridge, United Kingdom. From 1992 to 1996, he was a research assistant at the Microcomputing Laboratory (LAMI) and at the MANTRA Center for Neuro-Mimetic Systems of the EPFL. In December, 1996, he joined the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG). After working on datapath generation tools, he became head of the embedded memory unit in the Design Libraries division. Ienne was a recipient of the Best Paper Award at the 40th Design Automation Conference (DAC) in 2003, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) in 2007, at the 19th International Conference on Field-Programmable Logic and Applications (FPL) in 2009, and at the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) in 2012. In 2008, he has been general cochair of the 6th IEEE Symposium on Application Specific Processors (SASP) and guest editor of a special section on application specific processors which appeared in October 2008 on the IEEE Transactions on Very Large Scale Integration Systems. In 2010, he has been the program subcommittee chair of the Design Automation Conference (DAC) on High-Level and Logic Synthesis. From 2010 to 2012, he was a topic cochair of Design Automation and Test in Europe (DATE) for the Architectural and High-Level Synthesis topic. In 2011, he was a program cochair of the 20th IEEE Symposium on Computer Arithmetic (ARITH) and a program cochair of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). He is or has been a member of some fifty program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. Since 2011, he has been an associate editor of ACM Transactions on Design Automation of Electronic Systems (TODAES). His research interests include various aspects of computer and processor architecture, electronic design automation, computer arithmetic, FPGAs and reconfigurable computing, and multiprocessor systems-on-chip. He is a member of the IEEE and the IEEE Computer Society.