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Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning
July 2012 (vol. 61 no. 7)
pp. 1026-1039
ASCII Text
x 
 
Hoang Le, Viktor K. Prasanna, "Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning," IEEE Transactions on Computers, vol. 61, no. 7, pp. 1026-1039, July, 2012.
 
 
BibTex
x
 
@article{ 10.1109/TC.2011.130,
author = {Hoang Le and Viktor K. Prasanna},
title = {Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning},
journal ={IEEE Transactions on Computers},
volume = {61},
number = {7},
issn = {0018-9340},
year = {2012},
pages = {1026-1039},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.130},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning
IS - 7
SN - 0018-9340
SP1026
EP1039
EPD - 1026-1039
A1 - Hoang Le,
A1 - Viktor K. Prasanna,
PY - 2012
KW - IP Lookup
KW - longest prefix matching
KW - reconfigurable
KW - field-programmable gate array (FPGA)
KW - pipeline
KW - partitioning.
VL - 61
JA - IEEE Transactions on Computers
ER -
 
Hoang Le, University of Southern California, Los Angeles
Viktor K. Prasanna, University of Southern California, Los Angeles
Memory efficiency and dynamically updateable data structures for Internet Protocol (IP) lookup have regained much interest in the research community. In this paper, we revisit the classic tree-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely distributed routing tables, such as those potentially arising in the next-generation IPv6 routing protocol. Due to longer prefix lengths and much larger address space, preprocessing such routing tables for tree-based LPM can significantly increase the number of prefixes and/or memory stages required for IP lookup. We propose a prefix partitioning algorithm (DPP) to divide a given routing table into k groups of disjoint prefixes (k is given). The algorithm employs dynamic programming to determine the optimal split lengths between the groups to minimize the total memory requirement. Our algorithm demonstrates a substantial reduction in the memory footprint compared with those of the state of the art in both IPv4 and IPv6 cases. Two proposed linear pipelined architectures, which achieve high throughput and support incremental updates, are also presented. The proposed algorithm and architectures achieve a memory efficiency of 1 byte of memory for each byte of prefix for both IPv4 and IPv6. As a result, our design scales well to support either larger routing tables, longer prefix lengths, or both. The total memory requirement depends solely on the number of prefixes. Implementations on 45 nm ASIC and a state-of-the-art FPGA device (for a routing table consisting of 330K prefixes) show that our algorithm achieves 980 and 410 million lookups per second, respectively. These results are well suited for 100 Gbps lookup. The implementations also scale to support larger routing tables and longer prefix length when we go from IPv4 to IPv6. Additionally, the proposed architectures can easily interface with external SRAMs to ease the limitation of on-chip memory of the target devices.

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Index Terms:
IP Lookup, longest prefix matching, reconfigurable, field-programmable gate array (FPGA), pipeline, partitioning.
Citation:
Hoang Le, Viktor K. Prasanna, "Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning," IEEE Transactions on Computers, vol. 61, no. 7, pp. 1026-1039, July 2012, doi:10.1109/TC.2011.130
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