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High-Performance and Compact Architecture for Regular Expression Matching on FPGA
July 2012 (vol. 61 no. 7)
pp. 1013-1025
Yi-Hua Edward Yang, University of Southern California, Los Angeles
Viktor K. Prasanna, University of Southern California, Los Angeles
We present the design, implementation and evaluation of a high-performance architecture for regular expression matching (REM) on field-programmable gate array (FPGA). Each regular expression (regex) is first parsed into a concise token list representation, then compiled to a modular nondeterministic finite automaton (RE-NFA) using a modified version of the McNaughton-Yamada algorithm. The RE-NFA can be mapped directly onto a compact register-transistor level (RTL) circuit. A number of optimizations are applied to improve the circuit performance: 1) spatial stacking is used to construct an REM circuit processing m\ge 1 input characters per clock cycle; 2) single-character constrained repetitions are matched efficiently by parallel shift-register lookup tables; 3) complex character classes are matched by a BRAM-based classifier shared across regexes; 4) a multipipeline architecture is used to organize a large number of RE-NFAs into priority groups to limit the I/O size of the circuit. We implemented 2,630 unique PCRE regexes from Snort rules (February 2010) in the proposed REM architecture. Based on the place-and-route results from Xilinx ISE 11.1 targeting Virtex5 LX-220 FPGAs, the proposed REM architecture achieved up to 11 Gbps concurrent throughput for various regex sets and up to 2.67x the throughput efficiency of other state-of-the-art designs.

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Index Terms:
Regular expression, NFA, finite state machine, network intrusion detection, FPGA, BRAM, LUT, SRL.
Yi-Hua Edward Yang, Viktor K. Prasanna, "High-Performance and Compact Architecture for Regular Expression Matching on FPGA," IEEE Transactions on Computers, vol. 61, no. 7, pp. 1013-1025, July 2012, doi:10.1109/TC.2011.129
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