|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini, "Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications," IEEE Transactions on Computers, vol. 61, no. 7, pp. 939-953, July, 2012. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2011.127, author = {Francesco Paterna and Andrea Acquaviva and Alberto Caprara and Francesco Papariello and Giuseppe Desoli and Luca Benini}, title = {Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications}, journal ={IEEE Transactions on Computers}, volume = {61}, number = {7}, issn = {0018-9340}, year = {2012}, pages = {939-953}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.127}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications IS - 7 SN - 0018-9340 SP939 EP953 EPD - 939-953 A1 - Francesco Paterna, A1 - Andrea Acquaviva, A1 - Alberto Caprara, A1 - Francesco Papariello, A1 - Giuseppe Desoli, A1 - Luca Benini, PY - 2012 KW - Software/software engineering KW - operating systems KW - organization and design KW - real-time systems and embedded systems. VL - 61 JA - IEEE Transactions on Computers ER - | |||
[1] A. Acquaviva, L. Benini, and B. Riccò, “Software-Controlled Processor Speed Setting for Low-Power Streamingmultimedia,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 11, pp. 1283-1292, Nov. 2001.
[2] B. Bilgic, B. Horn, and I. Masaki, “Efficient Integral Image Computation on the GPU,” Proc. IEEE Intelligent Vehicles Symp., pp. 528-533, 2010.
[3] K.A. Bowman, A.R. Alameldeen, S.T. Srinivasan, and C.B. Wilkerson, “Impact of Die-to-Die and within-Die Parameter Variations on the Throughput Distribution of Multi-Core Processors,” Proc. ACM/IEEE Int'l Symp. Low Power Electronics and Design, pp. 50-55, 2007.
[4] Y. Cao and C. McAndrew, “Mosfet Modeling for 45 nm and Beyond,” Proc. IEEE Int'l Conf. Computer-Aided Design, pp. 638-643, 2007.
[5] S. Chandra, K. Lahiri, A. Raghunathan, and S. Dey, “System-on-Chip Power Management Considering Leakage Power Variations,” Proc. ACM/IEEE Design Automation Conf., pp. 877-882, 2007.
[6] A. Drake, R. Senger, H. Singh, G. Carpenter, and N. James, “Dynamic Measurement of Critical-Path Timing,” Proc. IEEE Conf. Integrated Circuit Design and Technology and Tutorial, pp. 249-252, 2008.
[7] S. Eyerman and L. Eeckhout, “A Counter Architecture for Online dvfs Profitability Estimation,” IEEE Trans. Computers, vol. 59, no. 11, pp. 1576-1583, Nov. 2010.
[8] P. Faraboschi, G. Brown, J.A. Fisher, G. Desoli, and F. Homewood, “Lx: A Technology Platform for Customizable Vliw Embedded Processing,” Proc. Conf. Int'l Symp. Computer Architecture, pp. 203-213, 2000.
[9] E. Flamand, “Strategic Directions Toward Multicore Application Specific Computing,” Proc. IEEE Conf. Design, Automation and Test in Europe, p. 1266, 2009.
[10] B.G. Haskell, A. Puri, and A.N. Netravali, Digital Video: An Introduction to MPEG-2. Chapman & Hall, Ltd., 1996.
[11] S. Herbert and D. Marculescu, “Characterizing Chip-Multiprocessor Variability-Tolerance,” Proc. ACM Conf. Design Automation Conf., pp. 313-318, 2008.
[12] S. Hong, S. Narayanan, and M. Kandemir, “Process Variation Aware Thread Mapping for Chip Multiprocessors,” Proc. IEEE Conf. Design, Automation and Test in Europe, pp. 821-826, 2009.
[13] L. Huang and Q. Xu, “Energy-Efficient Task Allocation and Scheduling for Multi-Mode Mpsocs under Lifetime Reliability Constraint,” Proc. IEEE Conf. Design, Automation, and Test in Europe, pp. 1584-1589, 2010.
[14] L. Huang, F. Yuan, and Q. Xu, “Lifetime Reliability-Aware Task Allocation and Scheduling for mpsoc Platforms,” Proc. IEEE Conf. Design, Automation and Test in Europe, pp. 51-56, 2009.
[15] E. Humenay, D. Tarjan, and K. Skadron, “Impact of Process Variations on Multicore Performance Symmetry,” Proc. Conf. Design, Automation and Test in Europe, pp. 1653-1658, 2007.
[16] H. Jeon, W.H. Lee, and S.W. Chung, “Load Unbalancing Strategy for Multi-Core Embedded Processors,” IEEE Trans. Computers, vol. 59, no. 10, pp. 1434-1440, Oct. 2010.
[17] MPEG Video Compression Standard, J.L. Mitchell, W.B. Pennebaker, C.E. Fogg, and D.J. Legall, eds. Chapman & Hall, Ltd., 1996.
[18] M. Mutyam, F. Wang, R. Krishnan, V. Narayanan, M. Kandemir, Y. Xie, and M.J. Irwin, “Process-Variation-Aware Adaptive Cache Architecture and Management,” IEEE Trans. Computers, vol. 58, pp. 865-877, July 2009.
[19] P. Ndai, S. Bhunia, A. Agarwal, and K. Roy, “Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput,” IEEE Trans. Computers, vol. 57, no. 7, pp. 940-951, July 2008.
[20] G. Palermo, C. Silvano, and V. Zaccaria, “Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures,” Proc. IEEE Conf. Asia and South Pacific Design Automation Conf., pp. 323-328, 2009.
[21] A. Papanicolaou, M. Miranda, P. Marchal, B. Dierickx, and F. Catthoor, “At Tape-Out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?,” Proc. IEEE Conf. Custom Integrated Circuits Conf., pp. 773-778, 2007.
[22] F. Paterna, A. Acquaviva, F. Papariello, G. Desoli, and L. Benini, “Variability-Tolerant Workload Allocation for mpsoc Energy Minimization under Real-Time Constraints,” Proc. IEEE Workshop Embedded Systems for Real-Time Multimedia, pp. 134-142, 2009.
[23] F. Paterna, A. Acquaviva, F. Papariello, G. Desoli, M. Olivieri, and L. Benini, “Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip,” Proc. IEEE Conf. Design, Automation and Test in Europe, pp. 906-909, 2009.
[24] M. Pittau, A. Alimonda, S. Carta, and A. Acquaviva, “Impact of Task Migration on Streaming Multimedia for Embedded Multiprocessors: A Quantitative Evaluation,” Proc. IEEE Workshop Embedded Systems for Real-Time Multimedia, pp. 59-64, 2007.
[25] B. Rebaud, M. Belleville, E. Beigne, M. Robert, P. Maurine, and N. Azemard, “An Innovative Timing Slack Monitor for Variation Tolerant Circuits,” Proc. IEEE Conf. IC Design and Technology, pp. 215-218, 2009.
[26] L. Singhal and E. Bozorgzadeh, “Process Variation Aware System-Level Task Allocation Using Stochastic Ordering of Delay Distributions,” Proc. IEEE Conf. Computer-Aided Design, pp. 570-574, 2008.
[27] D. Sylvester, D. Blaauw, and E. Karl, “Elastic: An Adaptive Self-Healing Architecture for Unpredictable Silicon,” IEEE Design and Test of Computers, vol. 23, no. 6, pp. 484-490, June 2006.
[28] R. Teodorescu and J. Torrellas, “Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors,” ACM SIGARCH Computer Architecture News, vol. 36, no. 3, pp. 363-374, 2008.
[29] A. Tiwari and J. Torrellas, “Facelift: Hiding and Slowing Down Aging in Multicores,” Proc. IEEE/ACM Int'l Symp. Microarchitecture, pp. 129-140, 2008.
[30] Vam—Variability Aware Modeling, http://www.imec.be/ ScientificReport/SR2007/ html1384291.html, 2011.
[31] N. Verghese, R. Rouse, and P. Hurat, “Predictive Models and CAD Methodology for Pattern Dependent Variability,” Proc. IEEE Conf. Asia and South Pacific Design Automation, pp. 213-218, 2008.
[32] F. Wang, C. Nicopoulos, X. Wu, Y. Xie, and N. Vijaykrishnan, “Variation-Aware Task Allocation and Scheduling for mpsoc,” Proc. IEEE Conf. Computer-Aided Design, pp. 598-603, 2007.
[33] L. Zhang, L.S. Bai, R.P. Dick, L. Shang, and R. Joseph, “Process Variation Characterization of Chip-Level Multiprocessors,” Proc. ACM Conf. Design Automation, pp. 694-697, 2009.

