The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.07 - July (2012 vol.61)
pp: 928-938
Wei-Lin Tsai , National Taiwan University, Taipei
Wei-Chih Liu , National Taiwan University, Taipei
James Chien-Mo Li , National Taiwan University, Taipei
ABSTRACT
This paper proposes four logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike existing scan chain fault models, depend on the previous scan inputs as well as primary inputs. A bridging pair extraction algorithm is proposed to quickly extract bridging pairs from the layout. The paper proposed two sets of structural reduction techniques so that runtime is very short. Experimental results on ISCAS benchmark circuits show that, on the average, logic-chain bridging faults can be diagnosed within an accuracy of four bridging pairs. The techniques are still applicable when there are only 10 failing patterns due to limited ATE failure memory. This paper demonstrates the feasibility to diagnose logic-chain bridging faults by software.
INDEX TERMS
Design for testability, diagnosis, scan.
CITATION
Wei-Lin Tsai, Wei-Chih Liu, James Chien-Mo Li, "Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis", IEEE Transactions on Computers, vol.61, no. 7, pp. 928-938, July 2012, doi:10.1109/TC.2011.98
REFERENCES
[1] S. Kundu, “Diagnosis Scan Chain Faults,” IEEE Trans. Very Large Scale Integration Systems, vol. 2, no. 4, pp. 512-516, Dec. 1994.
[2] K. Stanley, “High-Accuracy Flush-and-Scan Software Diagnostic,” IEEE Design and Test of Computers, vol. 18, no. 6, pp. 56-62, Nov./Dec. 2001.
[3] R. Guo and S. Venkataraman, “A New Technique for Scan Chain Failure Diagnosis,” Proc. Int'l Symp. Testing and Failure Analysis, pp. 723-732, 2002.
[4] Y. Huang, W.-T. Cheng, S.M. Reddy, C.-J. Hsieh, and Y.-T. Hung, “Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault,” Proc. IEEE Int'l Test Conf., pp. 319-327, 2003.
[5] P. Song, F. Stellari, T. Xia, and A. Weger, “A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current,” Proc. IEEE Int'l Test Conf., pp. 140-147, 2004.
[6] Y. Huang, W.-T. Cheng, N. Tamarapalli, J. Rajski, and R. Klingenberg, “Diagnosis with Limited Failure Information,” Proc. Int'l Test Conf., Oct. 2006.
[7] YeildAssist User's Guide, Software Version 8.2007_2, Mentor Graphics Corporation, May 2007.
[8] F. Motika, P. Nigh, P. Song, and H.B. Druckerman, “AC Scan Diagnostic Method,” US Patent 6,516,432 B1, Feb. 2003.
[9] C. Metra, M. Favalli, P. Olivo, and B. Ricco, “Testing og Resistive Bridging Faults in CMOS Flip-Flops,” Proc. European Test Conf., pp. 530-531, 1993.
[10] F. Yang, S. Chakravarty, N. Prasanna, S.M. Reddy, and I. Pomeranz, “Detectability of Internal Bridging Faults in Scan Chains,” Proc. Asian and South Pacific Design Automation Conf., pp. 678-683, 2009.
[11] Y. Huang, W. Hsu, Y-S. Chen, W.T. Cheng, and R. Guo, “Diagnose Compound Scan Chain and System Logic Defects,” Proc. IEEE Int'l Test Conf., 2007.
[12] Int'l Technology Roadmap for Semiconductors, http:/www.itrs. net/, 2011.
[13] R. Guo and S. Venkataraman, “A Technique for Fault Diagnosis of Defects in Scan Chains,” Proc. IEEE Int'l Test Conf., pp. 268-277, 2001.
[14] Y. Huang, R.-F. Guo, W.-T. Cheng, and J.C.-M. Li, “Survey of Scan Chain Diagnosis,” IEEE Design and Test of Computers, vol. 25, no. 3, pp. 240-248, May/June 2008.
[15] J. Hirase, N. Shindou, and K. Akahori, “Scan Chain Diagnosis Using IDDQ Current Measurement,” Proc. Eighth Asian Test Symp., pp. 153-157, 1999.
[16] Y. Huang, “Dynamic Learning Based Scan Chain Diagnosis,” Proc. Design and Test in Europe, pp. 510-515, 2007.
[17] Y. Huang, W.T. Cheng, and K.H. Tsai, “Diagnosing DACS (Defects that Affect Scan Chain and System Logic),” Proc. Int'l Symp. Testing and Failure Analysis, pp. 191-196, 2004.
[18] J.-S. Yang and S.-Y. Huang, “Quick Scan Chain Diagnosis Using Signal Profiling,” Proc. Int'l Conf. Computer Design, Oct. 2005.
[19] J.C.-M. Li, “Diagnosis of Single Stuck-at Faults and Multiple Timing Faults in Scan Chains,” IEEE Trans. Very Large Scale Integration Systems, vol. 13, no. 6, pp. 708-718, June 2005.
[20] Y.-L. Kao, W.-S. Chuang, and J. C-M Li, “Jump Simulation: A Fast and Precise Scan Chain Fault Diagnosis Technique,” Proc. IEEE Int'l Test Conf., Oct. 2006.
[21] S. Chakravarty and Y. Gong, “An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits,” Proc. Design Automation Conf., pp. 520-524, 1993.
[22] S.D. Millman, E.J. McCluskey, and J.M. Acken, “Diagnosing CMOS Bridgmg Faults with Stuck-at Fault Dictionaries,” Proc. Int'l Test Conf., pp. 860-870, 1990.
[23] B. Chess, D. Lavo, and T. Larrabee, “Diagnosis of Realistic Bridging Faults with Single Stuck-at Information,” Proc. IEEE Int'l Test Conf., 1995.
[24] D. Lavo and T. Larrabee, “Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis,” Proc. IEEE Int'l Test Conf., 1996.
[25] S. Venkataraman and K. Fuchs, “A Deductive Technique for Diagnosis of Bridging Faults,” Proc. Int'l Conf. Computer-Aided Design, pp. 562-567, 1997.
[26] F.J. Ferguson and J.P. Shen, “Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis,” Proc. IEEE Int'l Test Conf., pp. 475-484, 1988.
[27] Z. Stanojevic and D.M.H. Walker, “FedEx—A Fast Bridging Fault Extractor,” Proc. IEEE Int'l Test Conf., pp. 696-703, 2001.
[28] C. Sebeke, J.P. Teixeira, and M.J. Ohletz, “Automatic Fault Extraction and Simulation of Layout Realistic Faults for Integrated Analogue Circuits,” Proc. European Design and Test Conf., p. 464, 1995.
[29] T. Vogels, W. Maly, and R.D. Blanton, “Progressive Bridge Identification,” Proc. IEEE Int'l Test Conf., pp. 309-317, 2003.
[30] W. Zou, W.T. Cheng, and S.M. Reddy, “Bridge Defect Diagnosis with Physical Information,” Proc. IEEE Asian Test Symp., 2005.
[31] J.M. Acken and S.D. Millman, “Fault Model Evolution For Diagnosis: Accuracy vs Precision,” Proc. IEEE Custom Integrated Circuits Conf., 1992.
[32] K.C.Y. Mei, “Bridging and Stuck-at Faults,” IEEE Trans. Computers, vol. C-23, no. 7, pp. 720-727, July 1974.
[33] Y. Huang, W.-T. Cheng, C.-J. Hsieh, H.-Y. Tseng, A. Huang, and Y.-T. Hung, “Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis,” Proc. IEEE Design Automation and Test in Europe Conf., pp. 1530-1591, 2004.
[34] W.L. Tsai, “Structural Reduction Techniques for Fast Diagnosis of Logic-Chain Bridging Faults,” master's thesis, Nat'l Taiwan Univ., 2009.
[35] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability. Elsevier Science, July 2006.
[36] L.M. Huisman, Data Mining and Diagnosis of IC Fail. Springer Science, 2005.
[37] W.C. Liu, “Diagnosis of Logic-Chain Bridging Faults,” master's thesis, Nat'l Taiwan Univ., 2008.
[38] D. Lavo and T. Larrabee, “Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis,” Proc. IEEE Int'l Test Conf., 1996.
[39] S. Venkataraman and S.B. Drummonds, “Poirot: Applications of a Logic Fault Diagnosis Tool,” IEEE Design and Test Computers, vol. 18, no. 1, pp. 19-30, Jan./Feb. 2001.
[40] G.S. Greenstein and J.H. Patel, “E-PROOFS: A CMOS Bridging Fault Simulator,” Proc. IEEE/ACM Int'l Conf. Computer Aided Design (CAD), pp. 268-271, 1992.
[41] Y. Huang, W.-T. Cheng, C.-J. Hsieh, H.-Y. Tseng, A. Huang, and Y.-T. Hung, “Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults,” Proc. Asian Test Symp., 2003.
[42] J. Waicukauski and E. Lindbloom, “Failure Diagnosis of Structured VLSI,” IEEE Design and Test Computers, vol. 6, no. 4, pp. 49-60, Aug. 1989.
22 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool