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Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length
June 2012 (vol. 61 no. 6)
pp. 899-904
ASCII Text
x 
 
Irith Pomeranz, "Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length," IEEE Transactions on Computers, vol. 61, no. 6, pp. 899-904, June, 2012.
 
 
BibTex
x
 
@article{ 10.1109/TC.2011.107,
author = {Irith Pomeranz},
title = {Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length},
journal ={IEEE Transactions on Computers},
volume = {61},
number = {6},
issn = {0018-9340},
year = {2012},
pages = {899-904},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.107},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length
IS - 6
SN - 0018-9340
SP899
EP904
EPD - 899-904
A1 - Irith Pomeranz,
PY - 2012
KW - Functional test sequences
KW - stuck-at faults
KW - synchronous sequential circuits
KW - transition faults.
VL - 61
JA - IEEE Transactions on Computers
ER -
 
Irith Pomeranz, Purdue University, West Lafayette
Functional test sequences have several advantages over structural tests when they are applied at-speed. A large pool of functional test sequences may be available for a circuit due to the application of a simulation-based design verification process. This paper describes a versatile procedure that uses a pool of functional test sequences as a basis for forming a single compact functional test sequence that achieves the same or higher gate-level fault coverage than the given pool. The procedure extracts test subsequences from the test sequences in the pool and concatenates them to form a single test sequence. It also employs an enhanced static test compaction process aimed at improving the fault coverage in addition to reducing the test sequence length.

[1] P.C. Maxwell, R.C. Aitken, K.R. Kollitz, and A.C. Brown, “IDDQ and AC Scan: The War against Unmodelled Defects,” Proc. Int'l Test Conf., pp. 250-258, 1996.
[2] J. Rearick, “Too Much Delay Fault Coverage Is a Bad Thing,” Proc. Int'l Test Conf., pp. 624-633, 2001.
[3] J. Saxena, K.M. Butler, V.B. Jayaram, S. Kundu, N.V. Arvind, P. Sreeprakash, and M. Hachinger, “A Case Study of IR-Drop in Structured at-Speed Testing,” Proc. Int'l Test Conf., pp. 1098-1104, 2003.
[4] S. Sde-Paz and E. Salomon, “Frequency and Power Correlation between at-Speed Scan and Functional Tests,” Proc. IEEE Int'l Test Conf., pp. 1-9, 2008.
[5] T. Niermann and J.H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Conf. Design Automation, pp. 214-218, 1991.
[6] P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, “An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms,” Proc. Int'l Test Conf., pp. 240-249, 1994.
[7] E.M. Rudnick and J.H. Patel, “Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation,” Proc. Design Automation Conf., pp. 183-188, 1995.
[8] R. Guo, S.M. Reddy, and I. Pomeranz, “PROPTEST: A Property-Based Test Generator for Synchronous Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 22, no. 8, pp. 1080-1091, Aug. 2003.
[9] W.K. Lam, Hardware Design Verification: Simulation and Formal Method-Based Approaches. Prentice Hall, 2008.
[10] S. Park, L. Chen, P. Parvathala, S. Patil, and I. Pomeranz, “A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests,” Proc. IEEE Int'l Test Conf., pp. 1-10, 2006.
[11] I. Pomeranz, P.K. Parvathala, and S. Patil, “Estimating the Fault Coverage of Functional Test Sequences without Fault Simulation,” Proc. 16th Asian Test Symp., pp. 25-32, 2007.
[12] H. Fang, K. Chakrabarty, A. Jas, S. Patil, and C. Tirumurti, “RT-Level Deviation-Based Grading of Functional Test Sequences,” Proc. IEEE Very Large Scale Integration (VLSI) Test Symp., pp. 264-269, 2009.
[13] R.K. Roy, T.M. Niermann, J.H. Patel, J.A. Abraham, and R.A. Saleh, “Compaction of ATPG-Generated Test Sequences for Sequential Circuits,” Proc. Int'l Conf. Computer-Aided Design, pp. 382-385, 1988.
[14] F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, “New Static Compaction Techniques of Test Sequences for Sequential Circuits,” Proc. European Design and Test Conf., pp. 37-43, 1997.
[15] I. Pomeranz and S.M. Reddy, “On Static Compaction of Test Sequences for Synchronous Sequential Circuits,” Proc. Design Automation Conf., pp. 215-220, 1996.
[16] A. Sanyal, K. Chakrabarty, M. Yilmaz, and H. Fujiwara, “RT-Level Design-for-Testability and Expansion of Functional Test Sequences for Enhanced Defect Coverage,” Proc. IEEE Int'l Test Conf., pp. 1-10, 2010.
[17] I. Pomeranz and S.M. Reddy, “Vector Restoration Based Static Compaction Using Random Initial Omission,” IEEE Trans. Computer-Aided Design, vol. 23, no. 11, pp. 1587-1592, Nov. 2004.
[18] K.-T. Cheng, “Transition Fault Testing for Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 12, no. 12, pp. 1971-1983, Dec. 1993.

Index Terms:
Functional test sequences, stuck-at faults, synchronous sequential circuits, transition faults.
Citation:
Irith Pomeranz, "Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length," IEEE Transactions on Computers, vol. 61, no. 6, pp. 899-904, June 2012, doi:10.1109/TC.2011.107
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