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Issue No.06  June (2012 vol.61)
pp: 857869
Souradip Sarkar , Washington State University, Pullman
Partha Pratim Pande , Washington State University, Pullman
Turbo Majumder , Washington State University, Pullman
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.100
ABSTRACT
Maximum Parsimony phylogenetic tree reconstruction is based on finding the breakpoint median, given a set of species, and is represented by a bounded edgeweight graph model. This reduces the breakpoint median problem to one of solving multiple instances of the Traveling Salesman Problem (TSP), which is a classical NPcomplete problem in graph theory. Exponential time algorithms that apply efficient runtime heuristics, such as branchandbound, to dynamically prune the search space are used to solve TSP. In this paper, we present the design and performance evaluation of a networkonchip (NoC)based implementation for solving TSP under the bounded edgeweight model, as used in the computation of breakpoint phylogeny. Our approach takes advantage of finegrain parallelism from the multiple processing elements (PEs) and uses efficient NoC architecture for interPE communication. To accelerate the application on hardware, our PE design optimizes a particular lower bound calculation operation which typically tends to be the serial bottleneck in computation of a TSP solution. We also explore two representative NoC architectures—mesh and quadtree—and show that the latter is more energyefficient for this application domain. Experimental results show that this new implementation is able to achieve speedups of up to three orders of magnitude over stateoftheart multithreaded software implementations.
INDEX TERMS
Phylogenetics, breakpointmedian problem, maximum parsimony, traveling salesman problem.
CITATION
Souradip Sarkar, Partha Pratim Pande, Turbo Majumder, "NoCBased Hardware Accelerator for Breakpoint Phylogeny", IEEE Transactions on Computers, vol.61, no. 6, pp. 857869, June 2012, doi:10.1109/TC.2011.100
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