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Issue No.06 - June (2012 vol.61)
pp: 790-803
Julio Villalba Moreno , University of Malaga, Malaga
Tomas Lang , University of California at Irvine, Irvine
Javier Hormigo , University of Malaga, Malaga
ABSTRACT
In this paper, we present multioperand radix-2 online addition using different data representations (signed-digit, two's complement, and carry-save), in particular cases in which operands with different representations are added. We use the previously defined online full adder (olFA) as a component to build different multioperand online architectures. To merge data with different representations, an inner conversion of data is performed, eliminating any conversion stage and penalty time. We propose a technique to build multioperand trees efficiently and give six practical rules to deal with different kinds of data in the same adder. For addition of a stream of data, we determine the minimum number of separation cycles required to isolate two successive computations and propose a novel hardware technique that eliminates completely the separation cycles, resulting in the maximum throughput possible.
INDEX TERMS
Online addition, multioperand, signed-digit, carry-save.
CITATION
Julio Villalba Moreno, Tomas Lang, Javier Hormigo, "Radix-2 Multioperand and Multiformat Streaming Online Addition", IEEE Transactions on Computers, vol.61, no. 6, pp. 790-803, June 2012, doi:10.1109/TC.2011.97
REFERENCES
[1] A.C. Shantilal, A.F. Tenca, and M.H. Sinky, “Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications,” Proc. 15th IEEE Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP '04), July 2004.
[2] A. Avizienis, “Signed-Digit Number Representations for Fast Parallel Arithmetic,” IRE Trans. Electronic Computers, vol. EC-10, no. 3, pp. 389-400, Sept. 1961.
[3] M.D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann, 2004.
[4] R. Galli and A.F. Tenca, “A Design Methodology for Networks of Online Modules and Its Application to the Levinson-Durbin Algorithm,” IEEE Trans. Very Large Scale Integration Systems, vol. 12, no. 1, pp. 52-66, Jan. 2004.
[5] R. Galli and A.F. Tenca, “Design and Evaluation of On-Line Arithmetic for Signal Processing Applications on FPGAs,” Proc. SPIE -Advanced SIgnal Processing Algorithms, Architectures and Implemention XI, pp. 134-144, 2001.
[6] P. Kornerup, “Reviewing 4-to-2 Adders for Multi-Operand Addition,” Proc. IEEE Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP '02), July 2002.
[7] D. Lau, A. Schneider, M.D. Ercegovac, and J. Villasenor, “A FPGA Based Library for on Line Signal Processing,” J. VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 28, nos. 1/2, pp. 129-143, 2001.
[8] J. Olivares, J. Hormigo, J. Villalba, and I. Benavides, “Minimum Sum of Absolute Differences Implementation in a Single FPGA Device,” Proc. Field Programmable Logic and Application (FPL '04), pp. 985-990, Sept. 2004.
[9] D.S. Phatak, T. Goff, and I. Koren, “On Constant-Time Addition and Simultaneous Format Conversion Based On Redundant Binary Representation,” IEEE Trans. Computers, vol. 50, no. 11, pp. 1267-1278, Nov. 2001.
[10] A. Tisserand and M. Dimmler, “FPGA Implementation of Real-Time Digital Controllers Using Online Arithmetic,” Proc. Seventh Int'l Workshop Field-Programmable Logic and Applications, pp. 472-481, Aug. 1997.
[11] A. Tisserand, P. Marchal, and C. Piguet, “An On-Line Arithmetic Based FPGA for Low-Power Custom Computing,” Proc. Ninth Int'l Workshop Field-Programmable Logic and Applications (FPL '99), pp. 264-273, July/Aug. 1999.
[12] J. Villalba, J. Hormigo, J.M. Prades, and E.L. Zapata, “On-Line Multioperand Addition Based on Online Full Adders,” Proc. 16th IEEE Int'l Conf. Application-Specific Systems, Architecture Processors (ASAP '05), pp. 322-327, July 2005.
[13] J. Villalba, J. Hormigo, and E.L. Zapata, “Improving the Throughput of On-Line Addition for Data Streams,” Proc. 18th IEEE Int'l Conf. Application-Specific Systems, Architecture Processors (ASAP '07), pp. 272-277, July 2007.
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