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Issue No.05 - May (2012 vol.61)
pp: 676-685
Junfeng Fan , Katholieke Universiteit Leuven and IBBT, ESAT/SCD-COSIC, Leuven-Heverlee
Frederik Vercauteren , Katholieke Universiteit Leuven and IBBT, ESAT/SCD-COSIC, Leuven-Heverlee
Ingrid Verbauwhede , Katholieke Universiteit Leuven and IBBT, ESAT/SCD-COSIC, Leuven-Heverlee
ABSTRACT
This paper describes a new method to speed up {\hbox{\rlap{I}\kern 2.0pt{\hbox{F}}}}_p-arithmetic in hardware for pairing-friendly curves, such as the well-known Barreto-Naehrig (BN) curves. We explore the characteristics of the modulus defined by these curves and choose curve parameters such that {\hbox{\rlap{I}\kern 2.0pt{\hbox{F}}}}_p multiplication becomes more efficient. The proposed algorithm uses Montgomery reduction in a polynomial ring combined with a coefficient reduction phase using a pseudo-Mersenne number. As an application, we show that the performance of pairings on BN curves in hardware can be significantly improved, resulting in a factor 2.5 speedup compared with state-of-the-art hardware implementations.
INDEX TERMS
Pairing-friendly curves, modular reduction.
CITATION
Junfeng Fan, Frederik Vercauteren, Ingrid Verbauwhede, "Efficient Hardware Implementation of Fp-Arithmetic for Pairing-Friendly Curves", IEEE Transactions on Computers, vol.61, no. 5, pp. 676-685, May 2012, doi:10.1109/TC.2011.78
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