Issue No.05 - May (2012 vol.61)
Junhee Yoo , Syst.-LSI Div., Samsung Electron. Co. Ltd., Yongin, South Korea
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.66
Memory-intensive operations and their memory access latency are often the performance bottleneck in parallel applications. In this paper, we investigate the concept of active memory operation which is an active data processing operation performed on the memory side. Utilizing the active memory operation, we can replace multiple transactions of memory accesses over the on-chip network and related computations on the processor side with a smaller number of high-level transactions and computations on the memory side. To realize the concept, we have designed a special-purpose processor called active memory processor which is tightly coupled with the memory and executes the active memory operations. In our case studies, we have applied the concept to five real-world applications (parallelized JPEG, FFT, text indexing for data mining, histogram, and eikonal equation solver) running on a 36--tile architecture with 64 cores and four memory tiles and found that the proposed approach can improve performance by 20.5~ 259.3 percent.
network-on-chip, memory architecture, special-purpose processor, active memory processor, network-on-chip-based architecture, memory-intensive operation, memory access latency, active memory operation, active data processing operation, on-chip network, high level transactions, System-on-a-chip, Memory management, Random access memory, Registers, Generators, Prefetching, shared memory system., Active memory operation, network-on-chip, on-chip communication
Junhee Yoo, "Active Memory Processor for Network-on-Chip-Based Architecture", IEEE Transactions on Computers, vol.61, no. 5, pp. 622-635, May 2012, doi:10.1109/TC.2011.66