The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.05 - May (2012 vol.61)
pp: 607-621
Liu Han , University of Saskatchewan, Saskatoon
Dongdong Chen , University of Saskatchewan, Saskatoon
Seok-Bum Ko , University of Saskatchewan, Saskatoon
ABSTRACT
This paper presents the algorithm and architecture of the decimal floating-point (DFP) logarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP logarithm results for any one of the three DFP formats specified in the IEEE 754-2008 standard. In order to optimize the latency for the proposed design, we mainly integrate the following novel features: 1) using the redundant carry-save representation of the data path; 2) reducing the number of iterations by determining the number of initial iteration; and 3) retiming and balancing the delay of the proposed architecture. The proposed architecture is synthesized with STM 90-nm standard cell library and the results show that the critical path delay and the number of clock cycles of the proposed Decimal64 logarithmic converter are 1.55 ns (34.4 FO4) and 19, respectively, and the total hardware complexity is 43,572 NAND2 gates. The delay estimation results of the proposed architecture show that its latency is close to that of the binary radix-16 logarithmic converter, and that it has a significant decrease on latency compared with a recently published high performance CORDIC implementation.
INDEX TERMS
Decimal floating-point, decimal logarithmic converter, digit-recurrence algorithm, selection by rounding.
CITATION
Liu Han, Dongdong Chen, Seok-Bum Ko, "Improved Decimal Floating-Point Logarithmic Converter Based on Selection by Rounding", IEEE Transactions on Computers, vol.61, no. 5, pp. 607-621, May 2012, doi:10.1109/TC.2011.43
REFERENCES
[1] M.F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proc. IEEE 16th Symp. Computer Arithmetic (ARITH '16), pp. 104-111, June 2003.
[2] IEEE, Inc., IEEE 754-2008 Standard for Floating-Point Arithmetic, Aug. 2008.
[3] L.-K. Wang, M.A. Erle, C. Tsen, E.M. Schwarz, and M.J. Schulte, “A Survey of Hardware Designs for Decimal Arithmetic,” J. IBM Research and Development, vol. 54, no. 3, pp. 8:1-8:15, Mar./Apr. 2010.
[4] A.Y. Duale, M.H. Decker, H.-G. Zipperer, M. Aharoni, and T.J. Bohizic, “Decimal Floating-Point in z9: An Implementation and Testing Perspective,” J. IBM Research and Development, vol. 51, nos. 1/2, pp. 217-227, Jan.-Mar. 2007.
[5] L. Eisen, J.W.W.III, H.-W. Tast, N. Mading, J. Leenstra, S.M. Mueller, C. Jacobi, J. Preiss, E.M. Schwarz, and S.R. Carlough, “IBM POWER6 Accelerators: VMX and DFU,” J. IBM Research and Development, vol. 51, no. 6, pp. 663-683, Nov. 2007.
[6] E.M. Schwarz, J.S. Kapernick, and M.F. Cowlishaw, “Decimal Floating-Point Support on the IBM System z10 Processor,” J. IBM Research and Development, vol. 53, no. 1, pp. 4:1-4:10, Jan. 2009.
[7] J.M. Muller, Elementary Functions, Algorithms and Implementation. Birkhäuser Verlag, 2005.
[8] W.F. Wang and E. Goto, “Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers,” IEEE Trans. Computers, vol. 43, no. 3, pp. 278-294, Mar. 1994.
[9] M.J. Schulte and E.E. SwartzlanderJR., “Hardware Designs for Exactly Rounded Elementary Functions,” IEEE Trans. Computers, vol. 43, no. 8, pp. 964-973, Aug. 1994.
[10] M.J. Schulte and J.E. Stine, “Approximating Elementary Functions with Symmetric Bipartite Tables,” IEEE Trans. Computers, vol. 48, no. 8, pp. 842-847, Aug. 1999.
[11] F.D. Dinechin and A. Tisserand, “Multipartite Table Methods,” IEEE Trans. Computers, vol. 54, no. 3, pp. 842-847, Mar. 2005.
[12] A. Pińeiro, M.D. Ercegovac, and J.D. Bruguera, “High-Radix Logarithm with Selection By Rounding: Algorithm and Implementation,” J. VLSI Signal Processing Systems, vol. 40, no. 1, pp. 842-847, Mar. 2005.
[13] M.D. Ercegovac, T. Lang, and P. Montuschi, “Very High-Radix Division with Prescaling and Selection by Rounding,” IEEE Trans. Computers, vol. 43, no. 8, pp. 909-918, May 1994.
[14] T. Lang and P. Montuschi, “Very-High Radix Square Root with Prescaling and Rounding and a Combined Division/Square Root Unit,” IEEE Trans. Computers, vol. 48, no. 8, pp. 842-847, Aug. 1999.
[15] E. Antelo, T. Lang, and J.D. Bruguera, “Computation of $\sqrt{x/d}$ in a Very-High Radix Combined Division/Square-Root Unit with Scaling and Selection by Rounding,” IEEE Trans. Computers, vol. 47, no. 2, pp. 842-847, Feb. 1998.
[16] E. Antelo, T. Lang, and J. Bruguera, “High-Radix CORDIC Rotation Based on Selection by Rounding,” J. VLSI Signal Processing Systems, vol. 25, no. 2, pp. 141-153, June 2000.
[17] A. Pińeiro, M.D. Ercegovac, and J.D. Bruguera, “Algorithm and Architecture for Logarithm, Exponential, and Powering Computation,” IEEE Trans. Computers, vol. 53, no. 9, pp. 842-847, Sept. 2004.
[18] S.D. Trong, K. Helwig, and M. Loch, “Digital Circuit for Calculating a Logarithm of a Number,” US Patent 5,363,321, Nov. 1994.
[19] F. Nagao and M. Fuma, “Logarithmic Value Calculation Circuit,” US Patent 6,345,285, Feb. 2002.
[20] B.L. Hallse, “Digital Base-10 Logarithm Converter,” US Patent 6,587,070, July 2003.
[21] R.W. Allred, “Circuits, Systems, and Methods Implementing Approximations for Logarithm Inverse Logarithm, and Reciprocal,” US patent 7,171,435, Jan. 2007.
[22] A. Vaźquez, J. Villalba, and E. Antelo, “Computation of Decimal Transcendental Functions Using the CORDIC Algorithm,” Proc. IEEE 19th Symp. Computer Arithmetic (ARITH '19), pp. 179-186, June 2009.
[23] L. Imbert, J.M. Muller, and F. Rico, “A Radix-10 BKM Algorithm for Computing Transcendentals on Pocket Computers,” J. VLSI Signal Processing Systems, vol. 25, no. 2, pp. 179-186, June 2000.
[24] J. Harrison, “Decimal Transcendentals via Binary,” Proc. IEEE 19th Symp. Computer Arithmetic (ARITH '19), pp. 187-194, June 2009.
[25] D. Chen and Y. Choi, and D. Teng, and K. Wahid, and S. Ko, “A Novel Decimal-to-Decimal Logarithmic Converter,” Proc. IEEE Symp. Circuit and System (ISCAS '08), pp. 688-691, May 2008.
[26] D. Chen, Y. Zhang, Y. Choi, M.H. Lee, and S. Ko, “A 32-Bit Decimal Floating-Point Logarithmic Converter,” Proc. IEEE 19th Symp. Computer Arithmetic (ARITH '19), pp. 195-203, June 2009.
[27] M.F. Cowlishaw, “Densely Packed Decimal Encoding,” J. IEE Computers and Digital Techniques, vol. 149, no. 3, pp. 102-104, May 2002.
[28] M. Cornea, J. Harrison, C. Anderson, P.T.P. Tang, E. Schneider, and E. Gvozdev, “A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format,” IEEE Trans. Computers, vol. 58, no. 2, pp. 842-847, Feb. 2009.
[29] J. Detrey and F. de Dinechin, “Parameterized Floating-Point Logarithm and Exponential Functions for FPGAs,” J. Microprocessors and Microsystems, vol. 31, no. 8, pp. 842-847, Dec. 2007.
[30] V. Lefévre and J.M. Muller, and A. Tisserand, “Toward Correctly Rounded Transcendentals,” IEEE Trans. Computers, vol. 47, no. 11, pp. 842-847, Nov. 1998.
[31] V.G. Oklobdzija, “An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis,” IEEE Trans. Very Large Scale Integration Systems, vol. 2, no. 1, pp. 842-847, Mar. 1994.
[32] M.A. Erle and M.J. Schulte, “Decimal Multiplication via Carry-Save Addition,” Proc. IEEE 14th Int'l Conf. Application-Specific Systems, Architectures, and Processors (ASAP '03), pp. 348-358, June 2003.
[33] T. Lang and A. Nannarelli, “A Radix-10 Combinational Multiplier,” Proc. 40th Asilomar Conf. Signals, Systems and Computers (ACSSC '06), pp. 313-317, Nov. 2006.
[34] A. Vaźquez and E. Antelo, “Conditional Speculative Decimal Addition,” Proc. Seventh Conf. Real Numbers and Computers (RNC 7), pp. 47-57, July 2006.
[35] P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. Computers, vol. C-22, no. 8, pp. 786-793, Aug. 1973.
[36] J.-P. Deschamps, G.J.A. Bioul, and G.D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems. Wiley, 2006.
[37] STMicroelectronics, 90nm CMOS090 Design Platform, 2007.
[38] I. Sutherland, R. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, 1999.
[39] A. Pińeiro, “Algorithms and Architectures for Elementary Function Computationr,” PhD dissertation, Univ. of Santiago de Compostela, Spain, 2003.
[40] Intel Corporation, Using Decimal Floating-Point with Intel C++ Compiler, http://software.intel.com/en-us/articles using- decimal-floating-point-w ith-intel-c-compiler , 2010.
28 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool