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Issue No.02 - February (2012 vol.61)
pp: 284-288
Earl E. Swartzlander , University of Texas at Austin, Austin
Hani H.M. Saleh , Intel, Austin
This paper describes two fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an add-subtract unit. The FFT processors use "butterfly” operations that consist of multiplications, additions, and subtractions of complex valued data. Both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology, the fused FFT butterflies are about 15 percent faster and 30 percent smaller than a conventional implementation. Also the numerical results of the fused implementations are slightly more accurate, since they use fewer rounding operations.
Floating-point arithmetic, fused floating-point operations, fast Fourier transform, Radix-2 FFT butterfly, Radix-4 FFT butterfly.
Earl E. Swartzlander, Hani H.M. Saleh, "FFT Implementation with Fused Floating-Point Operations", IEEE Transactions on Computers, vol.61, no. 2, pp. 284-288, February 2012, doi:10.1109/TC.2010.271
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