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DMA++: On the Fly Data Realignment for On-Chip Memories
February 2012 (vol. 61 no. 2)
pp. 237-250
ASCII Text
x 
 
Nikola Vujic, Felipe Cabarcas, Marc Gonzalez, Alex Ramirez, Xavier Martorell, Eduard Ayguade, "DMA++: On the Fly Data Realignment for On-Chip Memories," IEEE Transactions on Computers, vol. 61, no. 2, pp. 237-250, February, 2012.
 
 
BibTex
x
 
@article{ 10.1109/TC.2010.255,
author = {Nikola Vujic and Felipe Cabarcas and Marc Gonzalez and Alex Ramirez and Xavier Martorell and Eduard Ayguade},
title = {DMA++: On the Fly Data Realignment for On-Chip Memories},
journal ={IEEE Transactions on Computers},
volume = {61},
number = {2},
issn = {0018-9340},
year = {2012},
pages = {237-250},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.255},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - DMA++: On the Fly Data Realignment for On-Chip Memories
IS - 2
SN - 0018-9340
SP237
EP250
EPD - 237-250
A1 - Nikola Vujic,
A1 - Felipe Cabarcas,
A1 - Marc Gonzalez,
A1 - Alex Ramirez,
A1 - Xavier Martorell,
A1 - Eduard Ayguade,
PY - 2012
KW - DMA
KW - multicores
KW - alignment
KW - SIMD units.
VL - 61
JA - IEEE Transactions on Computers
ER -
 
Nikola Vujic, Barcelona Supercomputing Center and Universitat Politecnica de Catalunya, Barcelona
Felipe Cabarcas, Barcelona Supercomputing Center, Barcelona and Universidad de Antioquia, Medellin
Marc Gonzalez, Barcelona Supercomputing Center and Universitat Politecnica de Catalunya, Barcelona
Alex Ramirez, Barcelona Supercomputing Center and Universitat Politecnica de Catalunya, Barcelona
Xavier Martorell, Barcelona Supercomputing Center and Universitat Politecnica de Catalunya, Barcelona
Eduard Ayguade, Barcelona Supercomputing Center and Universitat Politecnica de Catalunya, Barcelona
Multimedia extensions based on Single-Instruction Multiple-Data (SIMD) units are widespread. They have been used, for some time, in processors and accelerators (e.g., the Cell SPEs). SIMD units usually have significant memory alignment constraints in order to meet power requirements and design simplicity. This increases the complexity of the code generated by the compiler as, in the general case, the compiler cannot be sure of the proper alignment of data. For that, the ISA provides either unaligned memory load and store instructions, or a special set of instructions to perform realignments in software. In this paper, we propose a hardware realignment unit that takes advantage of the DMA transfers needed in accelerators with local memories. While the data are being transferred, it is realigned on the fly by our realignment unit, and stored at the desired alignment in the accelerator memory. This mechanism can help programmers to better organize data in the accelerator memory so that the accelerator can possibly access the data with no special instructions. Finally, the data are realigned properly also when put back to main memory. Our experiments with nine applications show that with our approach, the bandwidth of the DMA transfers is not penalized.

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Index Terms:
DMA, multicores, alignment, SIMD units.
Citation:
Nikola Vujic, Felipe Cabarcas, Marc Gonzalez, Alex Ramirez, Xavier Martorell, Eduard Ayguade, "DMA++: On the Fly Data Realignment for On-Chip Memories," IEEE Transactions on Computers, vol. 61, no. 2, pp. 237-250, Feb. 2012, doi:10.1109/TC.2010.255
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