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Issue No.02  February (2012 vol.61)
pp: 173186
Haridimos T. Vergos , University of Patras, Patras
Giorgos Dimitrakopoulos , University of West Macedonia, Kozani
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.261
ABSTRACT
Two architectures for modulo 2^n+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2^n+1 addition. This sparse approach is enabled by the introduction of the inverted circular idempotency property of the parallelprefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high operation speed. The second architecture unifies the design of modulo 2^n\pm 1 adders. It is shown that modulo 2^n+1 adders can be easily derived by straightforward modifications of modulo 2^n1 adders with minor hardware overhead.
INDEX TERMS
Modulo arithmetic, residue number system (RNS), parallelprefix carry computation, computer arithmetic, VLSI.
CITATION
Haridimos T. Vergos, Giorgos Dimitrakopoulos, "On Modulo 2^n+1 Adder Design", IEEE Transactions on Computers, vol.61, no. 2, pp. 173186, February 2012, doi:10.1109/TC.2010.261
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