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Haridimos T. Vergos, Giorgos Dimitrakopoulos, "On Modulo 2^n+1 Adder Design," IEEE Transactions on Computers, vol. 61, no. 2, pp. 173186, February, 2012.  
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@article{ 10.1109/TC.2010.261, author = {Haridimos T. Vergos and Giorgos Dimitrakopoulos}, title = {On Modulo 2^n+1 Adder Design}, journal ={IEEE Transactions on Computers}, volume = {61}, number = {2}, issn = {00189340}, year = {2012}, pages = {173186}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.261}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  On Modulo 2^n+1 Adder Design IS  2 SN  00189340 SP173 EP186 EPD  173186 A1  Haridimos T. Vergos, A1  Giorgos Dimitrakopoulos, PY  2012 KW  Modulo arithmetic KW  residue number system (RNS) KW  parallelprefix carry computation KW  computer arithmetic KW  VLSI. VL  61 JA  IEEE Transactions on Computers ER   
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