Subscribe
Issue No.02 - February (2012 vol.61)
pp: 164-172
Ashkan Hosseinzadeh Namin , University of Waterloo, Waterloo
Huapeng Wu , University of Windsor, Windsor
Majid Ahmadi , University of Windsor, Windsor
ABSTRACT
Normal basis has been widely used for the representation of binary field elements mainly due to its low-cost squaring operation. Optimal normal basis type II is a special class of normal basis exhibiting very low multiplication complexity and is considered as a safe choice for hardware implementation of cryptographic applications. In this paper, high-speed architectures for binary field multiplication using reordered normal basis are proposed, where reordered normal basis is referred to as a certain permutation of optimal normal basis type II. Complexity comparison shows that the proposed architectures are faster compared to previously presented architectures in the open literature using either an optimal normal basis type II or a reordered normal basis. One advantage of the new word-level architectures is that the critical path delay is a constant (not a function of word size). This enables the multipliers to operate at very high clock rates regardless of the field size or the number of words. Hardware implementation of some practical size multipliers for elliptic curve cryptography is also included.
INDEX TERMS
Finite field, binary field, optimal normal basis type II, reordered normal basis, multiplication algorithm, multiplier, hardware.
CITATION
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi, "High-Speed Architectures for Multiplication Using Reordered Normal Basis", IEEE Transactions on Computers, vol.61, no. 2, pp. 164-172, February 2012, doi:10.1109/TC.2010.218
REFERENCES
 [1] D. Hankerson, A. Menezes, and S. Vanstone, Guide to Elliptic Curve Cryptography, Springer, http://www.cacr.math.uwaterloo.caecc/, Dec. 2003. [2] Nat'l Inst. of Standards and Technology, Digital Signature Standards, FIPS Publication, 186-3, June 2009. [3] R. Lidl and H. Niederreiter, Introduction to Finite Fields and Their Applications, second ed., Cambridge Univ. Press, 1997. [4] IEEE Std 1363-2000, IEEE Standard Specifications for Public-Key Cryptography, Jan. 2000. [5] Am. Nat'l Standard Inst., "Public Key Cryptography for the Financial Services Industry, The Elliptic Curve Digital Signature Algorithm (ECDSA)," ANSI X9.62, 2005. [6] A.H. Namin, H. Wu, and M. Ahmadi, "A High Speed Word Level Finite Field Multiplier Using Reordered Normal Basis," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), pp. 3278-3281, May 2008. [7] S. Gao, J. von zur Gathen, D. Panario, and V. Shoup, "Algorithms for Exponentiation in Finite Fields," J. Symbolic Computation, vol. 29, pp. 879-889, 2000. [8] G.B. Agnew, R.C. Mullin, and S. Vanstone, "Fast Exponentiation in $GF({2^n})$ ," Proc. Workshop Theory and Application of Cryptographic Techniques, Advances in Cryptology (Eurocrypt '88), C.G. Gunther, ed., pp. 251-255, 1998. [9] R.C. Mullin and R.M. Wilson, "Optimal Normal Bases in GF($p^n$ )," Discrete Applied Math., vol. 22, pp. 149-161, 1989. [10] S. Gao and S. Vanstone, "On Orders of Optimal Normal Basis Generators," Math. Computation, vol. 64, no. 2, pp. 1227-1233, 1995. [11] H. Wu, M.A. Hasan, I.F. Blake, and S. Gao, "Finite Field Multiplier Using Redundant Representation," IEEE Trans. Computers, vol. 51, no. 11, pp. 1306-1316, Nov. 2002. [12] J.L. Massey and J.K. Omura, "Computational Method and Apparatus for Finite Field Arithmetic," US Patent 4587627, 1984. [13] G.B. Agnew, R.C. Mullin, I.M. Onyszchuck, and S.A. Vanstone, "An Implementation for a Fast Public-Key Cryptosystem," J. Cryptology, vol. 3, pp. 63-79, 1991. [14] T. Beth and Gollman, "Algorithm Engineering for Public Key Algorithms," IEEE J. Selected Areas in Comm., vol. 7, no. 4, pp. 458-465, May 1989. [15] M. Feng, "A VLSI Architecture for Fast Inversion in $GF(2^m)$ ," IEEE Trans. Computers, vol. 38, no. 10, pp. 1383-1386, Oct. 1989. [16] W. Geiselmann and D. Gollmann, "Symmetry and Duality in Normal Basis Multiplication," Proc. Applied Algebra, Algebraic Algorithms, and Error Correcting Codes Symp., pp. 230-238, July 1998. [17] L. Gao and G.E. Sobelman, "Improved VLSI Designs for Multiplication and Inversion in $GF(2^M)$ over Normal Bases," Proc. 13th Ann. IEEE Int'l ASIC/SOC Conf., pp. 97-101, 2000. [18] C.C. Wang, T.K. Truong, H.M. Shao, L.J. Deutsch, J.K. Omura, and I.S. Reed, "VLSI Architectures for Computing Multiplications and Inverses in $GF(2^m)$ ," IEEE Trans. Computers, vol. 34, no. 8, pp. 709-716, Aug. 1985. [19] A. Reyhani-Masoleh and M.A. Hasan, "A New Construction of Massey-Omura Parallel Multiplier over $GF(2^m)$ ," IEEE Trans. Computers, vol. 51, no. 5, pp. 511-520, May 2002. [20] C.K. Koc and B. Sunar, "Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields," IEEE Trans. Computers, vol. 47, no. 3, pp. 353-356, Mar. 1998. [21] M.A. Hasan, M.Z. Wang, and V.K. Bhargava, "A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields," IEEE Trans. Computers, vol. 42, no. 10, pp. 1278-1280, Oct. 1993. [22] H. Wu and M.A. Hasan, "Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields," IEEE Trans. Computers, vol. 47, no. 8, pp. 883-887, Aug. 1998. [23] A.H. Namin, H. Wu, and M. Ahmadi, "Comb Architectures for Finite Field Multiplication in $F_{2^m}$ ," IEEE Trans. Computers, vol. 56, no. 7, pp. 909-916, July 2007. [24] A. Reyhani-Masoleh and M.A. Hasan, "Efficient Digit-Serial Normal Basis Multipliers over GF$(2^m)$ ," IEEE Trans. Computers, Special Issue on Cryptographic Hardware and Embedded Systems, vol. 52, no. 4, pp. 428-439, Apr. 2003. [25] A. Reyhani-Masoleh and M.A. Hasan, "Low Complexity Word-Level Sequential Normal Basis Multipliers," IEEE Trans. Computers, vol. 54, no. 2, pp. 98-110, Feb. 2005. [26] A. Reyhani-Masoleh, "Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases," IEEE Trans. Computers, vol. 55, no. 1, pp. 34-47, Jan. 2006. [27] J.P. Uyemura, CMOS Logic Circuit Design. Kluwer Academic Publishers, Feb. 1999. [28] 0.18μm TSMC CMOS Technology, Standard Cell Library, Canadian Microelectronics Corporation, Sept. 1999. [29] A. Hosseinzaded, H. Wu, and M. Ahmadi, "A High-Speed Word Level Finite Field Multiplier in ${\hbox{\rlap{I}\kern 2.0pt{\hbox{F}}}}_{2^m}$ Using Redundant Representation," IEEE Trans. Very Large Scale Integration, vol. 17, no. 10, pp. 1546-1550, Oct. 2009.