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A Pattern Adaptive NAND Flash Memory Storage Structure
January 2012 (vol. 61 no. 1)
pp. 134-138
Seung-Ho Park, Samsung Electronics, Co.
Jung-Wook Park, Yonsei university, Seoul
Shin-Dug Kim, Yonsei University, Seoul
Charles C. Weems, University of Massachusetts, Amherst
To enhance performance of flash memory-based solid state disk (SSD), large logically chained blocks can be assembled by binding adjacent flash blocks across several flash memory chips. However, flash memory does not allow in-place overwriting and thus the operations that merge writes on these blocks suffer a visible decrease in performance. Furthermore, when small random writes are spread over the disk address space, performance tends to be degraded significantly. We thus present a technique to manage random writes efficiently to achieve stable SSD performance. In this paper, we propose a pattern adaptive SSD structure, which classifies access patterns as either random or sequential. The structure primarily consists of a write cache and a flash translation layer that separates groups of writes by access pattern (S-FTL). Separately managing the two types of write patterns enables greater parallelism and reduces the cost of large block management, thus enhancing the performance of the proposed SSD. Simulation experiments show that the proposed pattern adaptive structure can provide 39 percent decrease in extra flash block erase overhead on the average, and write performance can be improved by around 60 percent, compared with a basic FTL applied to existing parallel SSD structures.

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Index Terms:
Disk access pattern, flash translation layer, NAND flash memory, secondary storage, solid state disk.
Citation:
Seung-Ho Park, Jung-Wook Park, Shin-Dug Kim, Charles C. Weems, "A Pattern Adaptive NAND Flash Memory Storage Structure," IEEE Transactions on Computers, vol. 61, no. 1, pp. 134-138, Jan. 2012, doi:10.1109/TC.2010.212
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