The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.01 - January (2012 vol.61)
pp: 73-86
Deumji Woo , Seoul National University, Seoul
Minje Jun , Yonsei University, Seoul
ABSTRACT
The crossbar (also called bus matrix) solution is known as one of the most effective communication architectures for modern high-performance embedded systems. To make it even more effective, several topology synthesis methods have been proposed. They mostly generate a crossbar network in a cascaded fashion under the assumption that each crossbar switch is fully connected (i.e., each input has a connection to every output). This assumption often limits optimizing the area efficiency and/or performance of the network due to the unnecessary connections inside the crossbar switches. Some existing methods marginally improve their synthesis results by eliminating the unnecessary connections after the synthesis step. Such postprocessing approaches make sense since considering partially connected crossbar switches earlier in the synthesis flow can greatly increase the optimal topology search space, thereby increasing the runtime. However, the result from these postprocessing techniques is typically far inferior to that from the exhaustive search. In this work, we tackle such limitations of previous methods by introducing a heuristic method based on iterative switch merging. To the best of authors' knowledge, none of previous methods consider the partial connection of crossbar switches in the middle of the topology synthesis. Our experimental results prove the effectiveness of the proposed method by showing up to 30.35 percent of area saving against those methods that consider the partial connection only in a postprocess. The results also show the superiority of the proposed method against the existing topology synthesis methods, showing up to 49.09 percent area saving and synthesis time reduction by several orders of magnitude.
INDEX TERMS
System-on-Chip (SoC), crossbar, topology synthesis, partial connection, on-chip interconnection network.
CITATION
Deumji Woo, Minje Jun, "Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network", IEEE Transactions on Computers, vol.61, no. 1, pp. 73-86, January 2012, doi:10.1109/TC.2010.211
REFERENCES
[1] M. Jun, K. Bang, H.J. Lee, N. Chang, and E.Y. Chung, "Slack-Based Bus Arbitration Scheme for Soft Real-Time Constrained Embedded Systems," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '07), pp. 159-164, Jan. 2007.
[2] K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "LOTTERY-BUS: A New High-Performance Communication Architecture for System-On-Chip Designs," Proc. Ann. Design Automation Conf. (DAC '01), pp. 15-20, June 2001.
[3] B.C. Lin, G.W. Lee, J.D. Huang, and J.Y. Jou, "A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '07), pp. 165-170, Jan. 2007.
[4] M. Drini`c, D. Kirovski, S. Megerian, and M. Potkonjak, "Latency-Guided On-Chip Bus Network Design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2663-2673, Dec. 2006.
[5] W. Dally and B. Towels, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003.
[6] M. Loghi, F. Angiolini, D. Bertozzi, and L. Benini, "Analyzing On-Chip Communication in a MPSoC Environment," Proc. Conf. Design, Automation and Test in Europe (DATE '04), pp. 752-757, Feb. 2004.
[7] K.K. Ryu, E. Shin, and V.J. Mooney, "A Comparison of Five Different Multiprocessor SoC Bus Architectures," Proc. Euromicro Symp. Digital Systems Design '01, pp. 202-209, Sept. 2001.
[8] AMBA Designer User Guides, http://www.arm.com/products/solutionsAMBA_Designer.html , 2010.
[9] SonicsMX SMART Interconnect Solution, http://www.sonicsinc. comsonicsMX.htm, 2010.
[10] S. Murali, L. Benini, and G. De Micheli, "An Application-Specific Design Methodology for On-Chip Crossbar Generation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 7, pp. 1283-1296, July. 2007.
[11] S. Murali and G. De Micheli, "An Application-Specific Design Methodology for STbus Crossbar Generation," Proc. Conf. Design, Automation and Test in Europe (DATE '04), pp. 1176-1181, Mar. 2005.
[12] S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Constraint-Driven Bus Matrix Synthesis for MPSoC," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '06), pp. 30-35, Jan. 2006.
[13] S. Pasricha and N. Dutt, "COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC," Proc. Conf. Design, Automation and Test in Europe (DATE '06), pp. 700-705, Mar. 2006.
[14] S. Pasricha, N. Dutt, and F.J. Kurdahi, "Dynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '09), pp. 25-30, Feb. 2009.
[15] J. Yoo, S. Yoo, and K. Choi, "Communication Architecture Synthesis of Cascaded Bus Matrix," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '07), pp. 171-177, Jan. 2007.
[16] M. Jun, S. Yoo, and E.Y. Chung, "Mixed Integer Linear Programming-Based Optimal Topology Synthesis of Cascaded Crossbar Switches," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '08), pp. 583-588, Jan. 2008.
[17] J. Yoo, S. Yoo, and K. Choi, "Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus," IEEE Trans. Very Large Scale Integration Systems, vol. 17, no. 8, pp. 1034-1047, Aug. 2009.
[18] M. Jun, S. Yoo, and E.Y. Chung, "Topology Synthesis of Cascaded Crossbar Switches," IEEE Trans. Computers-Aided Design of Integrated Circuits and Systems, vol. 28, no. 6, pp. 926-930, June 2009.
[19] S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, and L. Raffo, "Designing Application-Specific Networks on Chips with Floorplan Information," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '06), pp. 355-362, Jan. 2006.
[20] K. Srinivasan, K.S. Chatha, and G. Konjevod, "Linear-Programming-Based Techniques for Synthesis of Network-On-Chip Architectures," IEEE Trans. Very Large Scale Integration Syntems, vol. 14, no. 4, pp. 407-420, Apr. 2006.
[21] K. Srinivasan, K.S. Chatha, and G. Konjevod, "An Automated Technique for Topology and Route Generation of Application Specific On-Chip Interconnection Networks," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '05), pp. 231-237, Nov. 2005.
[22] K.S. Chatha, K. Srinivasan, and G. Konjevod, "Automated Techniques for Synthesis of Application-Specific Network-On-Chip Architectures," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1425-1438, Aug. 2008.
[23] S.N. Adya and I.L. Markov, "Fixed-Outline Floorplanning: Enabling Hierarchical Design," IEEE Trans. Very Large Scale Integration Systems, vol. 11, no. 6, pp. 1120-1135, Dec. 2003.
[24] L. Carloni, A.B. Kahng, S. Muddu, A. Pinto, K. Samadi, and P. Shama, "Interconnect Modeling for Improved System-Level Design Optimization," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '08), pp. 258-264, 2008.
[25] J.Z. Yan and C. Chu, "DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanner," Proc. Ann. Design Automation Conf. (DAC '08), pp. 167-172, 2008.
[26] S. Murali and G. De Micheli, "SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs," Proc. Ann. Design Automation Conf. (DAC '04), pp. 914-919, June 2004.
[27] S. Yan and B. Lin, "Application-Specific Network-On-Chip Architecture Synthesis Based on Set Partitions and Steiner Trees," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '08), pp. 277-282, 2008.
21 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool