Issue No.01 - January (2012 vol.61)
Manish Kumar Jaiswal , Indian Institute of Technology, Madras
Nitin Chandrachoodan , Indian Institute of Technology, Madras
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.24
Decomposition of a matrix into lower and upper triangular matrices (LU decomposition) is a vital part of many scientific and engineering applications, and the block LU decomposition algorithm is an approach well suited to parallel hardware implementation. This paper presents an approach to speed up implementation of the block LU decomposition algorithm using FPGA hardware. Unlike most previous approaches reported in the literature, the approach does not assume the matrix can be stored entirely on chip. The memory accesses are studied for various FPGA configurations, and a schedule of operations for scaling well is shown. The design has been synthesized for FPGA targets and can be easily retargeted. The design outperforms previous hardware implementations, as well as tuned software implementations including the ATLAS and MKL libraries on workstations.
LU decomposition, block LU, FPGA, hardware acceleration, floating point arithmetics, single/double precision, scaling, ATLAS, Intel-MKL, GPU.
Manish Kumar Jaiswal, Nitin Chandrachoodan, "FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture", IEEE Transactions on Computers, vol.61, no. 1, pp. 60-72, January 2012, doi:10.1109/TC.2011.24