
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Valeria Garofalo, Nicola Petra, Ettore Napoli, "Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error," IEEE Transactions on Computers, vol. 60, no. 9, pp. 13661371, September, 2011.  
BibTex  x  
@article{ 10.1109/TC.2010.236, author = {Valeria Garofalo and Nicola Petra and Ettore Napoli}, title = {Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error}, journal ={IEEE Transactions on Computers}, volume = {60}, number = {9}, issn = {00189340}, year = {2011}, pages = {13661371}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.236}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error IS  9 SN  00189340 SP1366 EP1371 EPD  13661371 A1  Valeria Garofalo, A1  Nicola Petra, A1  Ettore Napoli, PY  2011 KW  Multiplication KW  truncated multipliers KW  digital arithmetic KW  error compensation KW  error analysis KW  maximum error. VL  60 JA  IEEE Transactions on Computers ER   
[1] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford Univ. Press, 1999.
[2] V. Garofalo, “Truncated Binary Multipliers with Minimum Mean Square Error: Analytical Characterization, Circuit Implementation and Applications,” PhD dissertation, http://www.die.unina.it/dottoratoIET/tesi Garofalo_Tesi.pdf, 2009.
[3] Y.C. Lim, “SinglePrecision Multiplier with Reduced Circuit Complexity for Signal Processing Applications,” IEEE Trans. Computers, vol. 41, no. 10, pp. 13331336, Oct. 1992.
[4] J.H. Tu and L.D. Van, “PowerEfficient Pipelined Reconfigurable FixedWidth BaughWooley Multipliers,” IEEE Trans. Computers, vol. 58, no. 10, pp. 13461355, Oct. 2009.
[5] M.J. Schulte and K.E. Wires, “HighSpeed Inverse Square Roots,” Proc. 14th IEEE Symp. Computer Arithmetic, pp. 124131, 1999.
[6] R. Michard, A. Tisserand, and N. VeyratCharvillon, “Carry Prediction and Selection for Truncated Multiplication,” Proc. IEEE Workshop Signal Processing Systems Design and Implementation (SIPS '06), pp. 339344, Oct. 2006.
[7] M.J. Schulte and E.E. SwartzlanderJr., “Truncated Multiplication with Correction Constant [for DSP],” Proc. Sixth Workshop Very LargeScale Integration (VLSI) Signal Processing, pp. 388396, Oct. 1993.
[8] E.J. King and E.E. SwartzlanderJr., “DataDependent Truncation Scheme for Parallel Multipliers,” Proc. 31st Asilomar Conf. Signals, Systems and Computers, pp. 11781182, Nov. 1997.
[9] J.M. Jou, S.R. Kuang, and R.D. Chen, “Design of LowError FixedWidth Multipliers for DSP Applications,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 6, pp. 836842, June 1999.
[10] F. Curticapean and J. Niittylahti, “A Hardware Efficient Direct Digital Frequency Synthesizer,” Proc. Eighth IEEE Int'l Conf. Electronics, Circuits and Systems, (ICECS '01), vol. 1, pp. 5154, Sept. 2001.
[11] L.D. Van, S.S. Wang, and W.S. Feng, “Design of the Lower Error FixedWidth Multiplier and Its Application,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 10, pp. 11121118, Oct. 2000.
[12] L.D. Van and C.C. Yang, “Generalized LowError AreaEfficient FixedWidth Multipliers,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 52, no. 8, pp. 16081619, Aug. 2005.
[13] Y.C. Liao, H.C. Chang, and C.W. Liu, “Carry Estimation for Two's Complement FixedWidth Multipliers,” Proc. IEEE Workshop Signal Processing Systems Design and Implementation (SIPS '06), pp. 345350, Oct. 2006.
[14] S.R. Kuang and J.P. Wang, “LowError Configurable Truncated Multipliers for MultiplyAccumulate Applications,” Electronics Letters, vol. 42, no. 16, pp. 904905, Mar. 2006.
[15] A.G.M. Strollo, N. Petra, and D. De Caro, “DualTree Error Compensation for High Performance FixedWidth Multipliers,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 52, no. 8, pp. 501507, Aug. 2005.
[16] N. Petra, D. De Caro, and A.G.M. Strollo, “Design of FixedWidth Multipliers with Minimum Mean Square Error,” Proc. 18th European Conf. Circuit Theory and Design (ECCTD '07), pp. 464467, Aug. 2007.
[17] N. Petra, D. De Caro, V. Garofalo, E. Napoli, and A. Strollo, “Truncated Binary Multipliers with Variable Correction and Minimum Mean Square Error,” accepted for publication in IEEE Trans. Circuits and Systems I, vol. 57, no. 6, Sept. 2009.
[18] D. De Caro, E. Napoli, and A.G.M. Strollo, “Direct Digital Frequency Synthesizers with Polynomial Hyperfolding Technique,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 51, no. 7, pp. 337344, July 2004.
[19] N. Mukherjee, J. Rajski, and J. Tyszer, “Design of Testable Multipliers for FixedWidth Data Paths,” IEEE Trans. Computers, vol. 46, no. 7, pp. 795810, July 1997.
[20] J. Um and T. Kim, “Optimal BitLevel Arithmetic Optimisation for HighSpeed Circuits,” Electronics Letters, vol. 36, no. 5, pp. 405407, Mar. 2000.