The Community for Technology Leaders
Subscribe
Issue No.09 - September (2011 vol.60)
pp: 1366-1371
Valeria Garofalo , University of Napoli, Napoli
Nicola Petra , University of Napoli, Napoli
Ettore Napoli , University of Napoli, Napoli
ABSTRACT
A truncated multiplier is a multiplier with two n bit operands that produces a n bit result. Truncated multipliers discard some of the partial products of a complete multiplier to trade off accuracy with hardware cost. Compared with a conventional multiplier, a truncated multiplier introduces an error on the output whose magnitude depends on the input bits. The maximum value of the error is hardly computable, since it isn't possible to test every possible input and nonexhaustive simulations are very unlikely to provide the actual maximum absolute error value. It is therefore extremely useful to develop methods that provide the maximum error for a truncated multiplier. This paper presents a closed form analytical calculation, for every bit width, of the maximum error for a previously proposed family of truncated multipliers. The considered family of truncated multipliers is particularly important since it is proved to be the design that gives the lowest mean square error for a given number of discarder partial products. With the contribution of this paper, the considered family of truncated multipliers is the only architecture that can be designed, for every bit width, using an analytical approach that allows the a priori knowledge of the maximum error.
INDEX TERMS
Multiplication, truncated multipliers, digital arithmetic, error compensation, error analysis, maximum error.
CITATION
Valeria Garofalo, Nicola Petra, Ettore Napoli, "Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error", IEEE Transactions on Computers, vol.60, no. 9, pp. 1366-1371, September 2011, doi:10.1109/TC.2010.236
REFERENCES
 [1] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford Univ. Press, 1999. [2] V. Garofalo, “Truncated Binary Multipliers with Minimum Mean Square Error: Analytical Characterization, Circuit Implementation and Applications,” PhD dissertation, http://www.die.unina.it/dottoratoIET/tesi Garofalo_Tesi.pdf, 2009. [3] Y.C. Lim, “Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications,” IEEE Trans. Computers, vol. 41, no. 10, pp. 1333-1336, Oct. 1992. [4] J.-H. Tu and L.-D. Van, “Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers,” IEEE Trans. Computers, vol. 58, no. 10, pp. 1346-1355, Oct. 2009. [5] M.J. Schulte and K.E. Wires, “High-Speed Inverse Square Roots,” Proc. 14th IEEE Symp. Computer Arithmetic, pp. 124-131, 1999. [6] R. Michard, A. Tisserand, and N. Veyrat-Charvillon, “Carry Prediction and Selection for Truncated Multiplication,” Proc. IEEE Workshop Signal Processing Systems Design and Implementation (SIPS '06), pp. 339-344, Oct. 2006. [7] M.J. Schulte and E.E. SwartzlanderJr., “Truncated Multiplication with Correction Constant [for DSP],” Proc. Sixth Workshop Very Large-Scale Integration (VLSI) Signal Processing, pp. 388-396, Oct. 1993. [8] E.J. King and E.E. SwartzlanderJr., “Data-Dependent Truncation Scheme for Parallel Multipliers,” Proc. 31st Asilomar Conf. Signals, Systems and Computers, pp. 1178-1182, Nov. 1997. [9] J.M. Jou, S.R. Kuang, and R.D. Chen, “Design of Low-Error Fixed-Width Multipliers for DSP Applications,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 6, pp. 836-842, June 1999. [10] F. Curticapean and J. Niittylahti, “A Hardware Efficient Direct Digital Frequency Synthesizer,” Proc. Eighth IEEE Int'l Conf. Electronics, Circuits and Systems, (ICECS '01), vol. 1, pp. 51-54, Sept. 2001. [11] L.-D. Van, S.-S. Wang, and W.-S. Feng, “Design of the Lower Error Fixed-Width Multiplier and Its Application,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 10, pp. 1112-1118, Oct. 2000. [12] L.D. Van and C.-C. Yang, “Generalized Low-Error Area-Efficient Fixed-Width Multipliers,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 52, no. 8, pp. 1608-1619, Aug. 2005. [13] Y.-C. Liao, H.-C. Chang, and C.-W. Liu, “Carry Estimation for Two's Complement Fixed-Width Multipliers,” Proc. IEEE Workshop Signal Processing Systems Design and Implementation (SIPS '06), pp. 345-350, Oct. 2006. [14] S.-R. Kuang and J.-P. Wang, “Low-Error Configurable Truncated Multipliers for Multiply-Accumulate Applications,” Electronics Letters, vol. 42, no. 16, pp. 904-905, Mar. 2006. [15] A.G.M. Strollo, N. Petra, and D. De Caro, “Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 52, no. 8, pp. 501-507, Aug. 2005. [16] N. Petra, D. De Caro, and A.G.M. Strollo, “Design of Fixed-Width Multipliers with Minimum Mean Square Error,” Proc. 18th European Conf. Circuit Theory and Design (ECCTD '07), pp. 464-467, Aug. 2007. [17] N. Petra, D. De Caro, V. Garofalo, E. Napoli, and A. Strollo, “Truncated Binary Multipliers with Variable Correction and Minimum Mean Square Error,” accepted for publication in IEEE Trans. Circuits and Systems I, vol. 57, no. 6, Sept. 2009. [18] D. De Caro, E. Napoli, and A.G.M. Strollo, “Direct Digital Frequency Synthesizers with Polynomial Hyperfolding Technique,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 51, no. 7, pp. 337-344, July 2004. [19] N. Mukherjee, J. Rajski, and J. Tyszer, “Design of Testable Multipliers for Fixed-Width Data Paths,” IEEE Trans. Computers, vol. 46, no. 7, pp. 795-810, July 1997. [20] J. Um and T. Kim, “Optimal Bit-Level Arithmetic Optimisation for High-Speed Circuits,” Electronics Letters, vol. 36, no. 5, pp. 405-407, Mar. 2000.
FULL ARTICLE
7 ms
(Ver 2.0)

Marketing Automation Platform