Issue No.09 - September (2011 vol.60)
Ming Gao , UC Santa Barbara, Santa Barbara
Hsiu-Ming (Sherman) Chang , UC Santa Barbara, Santa Barbara
Peter Lisherness , UC Santa Barbara, Santa Barbara
Kwang-Ting (Tim) Cheng , UC Santa Barbara, Santa Barbara
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.34
There is a growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, their area overhead remains too high for cost-sensitive applications. In this paper, we introduce a Time-Multiplexed Online Checking (TMOC) scheme using embedded field-programmable blocks for checker implementation, which enables various system parts to be checked dynamically in-field in a time-multiplexed fashion. The test quality analyses using a probabilistic model show that TMOC could maintain high fault coverage that is similar to traditional dedicated checkers. We conducted a case study of an H.264 decoder design that demonstrates our TMOC scheme provides a significant reduction in chip area and power overhead for online checkers at the cost of increased fault detection latency. We have successfully implemented and demonstrated our proposed TMOC scheme using a single Field-Programmable Gate Array (FPGA) chip.
Availability, built-in tests, error-checking, fault tolerance.
Ming Gao, Hsiu-Ming (Sherman) Chang, Peter Lisherness, Kwang-Ting (Tim) Cheng, "Time-Multiplexed Online Checking", IEEE Transactions on Computers, vol.60, no. 9, pp. 1300-1312, September 2011, doi:10.1109/TC.2011.34