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Saeed Shamshiri, KwangTing (Tim) Cheng, "Modeling Yield, Cost, and Quality of a SpareEnhanced Multicore Chip," IEEE Transactions on Computers, vol. 60, no. 9, pp. 12461259, September, 2011.  
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@article{ 10.1109/TC.2011.32, author = {Saeed Shamshiri and KwangTing (Tim) Cheng}, title = {Modeling Yield, Cost, and Quality of a SpareEnhanced Multicore Chip}, journal ={IEEE Transactions on Computers}, volume = {60}, number = {9}, issn = {00189340}, year = {2011}, pages = {12461259}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.32}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Modeling Yield, Cost, and Quality of a SpareEnhanced Multicore Chip IS  9 SN  00189340 SP1246 EP1259 EPD  12461259 A1  Saeed Shamshiri, A1  KwangTing (Tim) Cheng, PY  2011 KW  Fault tolerance KW  redundant design KW  reliability KW  system on a chip KW  yield and cost modeling. VL  60 JA  IEEE Transactions on Computers ER   
[1] L. Hammond, B.A. Nayfeh, and K. Olukotun, “A SingleChip Multiprocessor,” Computer, vol. 30, no. 9, pp. 7985, Sept. 1997.
[2] M. Gschwind, H.P. Hofstee, B. Flachs, M. Hopkins, Y. Watanabe, and T. Yamazaki, “Synergistic Processing in Cell's Multicore Architecture,” IEEE Micro, vol. 26, no. 2, pp. 1024, Mar./Apr. 2006.
[3] R. Kumar, D.M. Tullsen, N.P. Jouppi, and P. Ranganathan, “Heterogeneous Chip Multiprocessors,” Computer, vol. 38, no. 11, pp. 3238, Nov. 2005.
[4] D. Pham et al., “The Design and Implementation of a FirstGeneration CELL Processor—A MultiCore SoC,” Proc. Int'l Conf. Integrated Circuit Design and Technology, pp. 4952, 2005.
[5] S. Vangal et al., “An 80Tile 1.28TFLOPS NetworkonChip in 65nm CMOS,” Proc. IEEE Int'l SolidState Circuits Conf., pp. 98589, 2007.
[6] T. Hsieh, K. Lee, and M.A. Breuer, “An ErrorOriented Test Methodology to Improve Yield with ErrorTolerance,” Proc. IEEE 24th VLSI Test Symp., pp. 130135, 2006.
[7] Int'l Technology Roadmap for Semiconductors, http://www.itrs.net/Links/2006Update2006UpdateFinal.htm . 2006.
[8] I. Koren and Z. Koren, “Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis,” Proc. IEEE, vol. 86, no. 9, pp. 18191837, Sept. 1998.
[9] R.T. Smith, J.D. Chlipala, J.F.M. Bindels, R.G. Nelson, F.H. Fischer, and T.F. Mantz, “Laser Programmable Redundancy and Yield Improvement in a 64K DRAM,” IEEE J. SolidState Circuits, vol. 16, no. 5, pp. 506514, Oct. 1981.
[10] J.H. Kim and S.M. Reddy, “On the Design of FaultTolerant TwoDimensional Systolic Arrays for Yield Enhancement,” IEEE Trans. Computers, vol. 38, no. 4, pp. 515525, Apr. 1989.
[11] F. Hatori et al., “Introducing Redundancy in Field Programmable Gate Arrays,” Proc. IEEE Custom Integrated Circuits Conf., pp. 7.1.17.1.4, 1993.
[12] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F.P. Higgins, and J.L. Lewandowski, “Built in Self Repair for Embedded High Density SRAM,” Proc. Int'l Test Conf., pp. 11121119, 1998.
[13] S. Makar, T. Altinis, N. Patkar, and J. Wu, “Testing of Vega2, a Chip MultiProcessor with Spare Processors,” Proc. IEEE Int'l Test Conf., pp. 110, 2007.
[14] S. Shamshiri, P. Lisherness, S.J. Pan, and K.T. (Tim) Cheng, “A Cost Analysis Framework for MultiCore Systems with Spares,” Proc. IEEE Int'l Test Conf. (ITC), pp. 18, 2008.
[15] S. Shamshiri and K.T. (Tim) Cheng, “Yield and Cost Analysis of a Reliable NoC,” Proc. IEEE 27th VLSI Test Symp. (VTS '09), pp. 173178, 2009.
[16] G. De Micheli and L. Benini, Networks on Chips. Morgan Kaufmann Publishers, 2006.
[17] T. Lehtonen, P. Liljeberg, and J. Plosila, “SelfTimed NoC Links Using Combinations of Fault Tolerance Methods,” Proc. IEEE Design Automation and Test in Europe, 2007.
[18] M.C. Neuenhahn, D. Lemmer, H. Blume, and T.G. Noll, “Quantitative Cost Modeling of Error Protection for NetworkonChip,” Proc. ProRISK Workshop, pp. 331337, 2007.
[19] Y. Jiao, Y. Yang, M. He, M. Yang, and Y. Jiang, “MultiPath Routing for Mesh/TorusBased NoCs,” Proc. Fourth Int'l Conf. Information Technology, (ITNG '07), pp. 734742, 2007.
[20] M. Gao, H.M. Chang, P. Lisherness, and K.T. (Tim) Cheng, “TimeMultiplexed Online Checking: A Feasibility Study,” Proc. Asian Test Symp. (ATS '08), pp. 371376, 2008.
[21] A. Krstic, W.C. Lai, L. Chen, K.T. (Tim) Cheng, and S. Dey, “Embedded SoftwareBased SelfTesting for SoC Design,” Proc. Design Automation Conf., pp. 355360, 2002.
[22] L. Chen and S. Dey, “SoftwareBased SelfTesting Methodology for Processor Cores,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 20, no. 3, pp. 369380, Mar. 2001.
[23] N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, and Y. Zorian, “Application and Analysis of RTLevel SoftwareBased SelfTesting for Embedded Processor Cores,” Proc. Int'l Test Conf. (ITC), pp. 431440, 2003.
[24] M. Nicolaidis and Y. Zorian, “OnLine Testing for VLSI—A Compendium of Approaches,” J. Electronic Testing, vol. 12, nos. 1/2, pp. 720, 1998.
[25] H. AlAsaad, B.T. Murray, and J.P. Hayes, “Online BIST for Embedded Systems,” IEEE Design & Test of Computers, vol. 15, no. 4, pp. 1724, Oct.Dec. 1998.
[26] M.A. Breuer and A.A. Ismaeel, “Roving Emulation as a Fault Detection Mechanism,” IEEE Trans. Computers, vol. 35, no. 11, pp. 933939, Nov. 1986.
[27] A.W. Righter, C.F. Hawkins, J.M. Soden, and P.C. Maxwell, “CMOS IC Reliability Indicators and Burnin Economics,” Proc. Int'l Test Conf., pp. 194203, 1998.
[28] T.R. Henry and T. Soo, “Burnin Elimination of a High Volume Microprocessor Using ${\rm I_{DDQ}}$ ,” Proc. Int'l Test Conf., pp. 242249, 1996.
[29] R. Kawahara, O. Nakayama, and T. Kurasawa, “The Effectiveness of ${\rm I_{DDQ}}$ and High Voltage Stress for Burnin Elimination CMOS Production,” Proc. IEEE Int'l Workshop IDDQ Testing, pp. 913, 1996.
[30] M. Sachdev, “Deep SubMicron IDDQ Testing: Issues and Solutions” Proc. European Design and Test Conf., 1997.
[31] K. Roy, T.M. Mak, and K.T. (Tim) Cheng, “Test Consideration for NanometerScale CMOS Circuits,” IEEE Design & Test of Computers, vol. 23, no. 2, pp. 128136, Mar.Apr. 2006.
[32] K.T. Cheng, S. Dey, M. Rodgers, and K. Roy, “Test Challenges for Deep SubMicron Technologies,” Proc. 37th Design Automation Conf., pp. 142149, 2000.
[33] J.T. De Sousa and V.D. Agrawal, “Reducing the Complexity of Defect Level Modeling Using the Clustering Effect,” Proc. Design, Automation and Test in Europe Conf. and Exhibition, pp. 640644, 2000.
[34] W. Kuo and T. Kim, “An Overview of Manufacturing Yield and Reliability Modeling for Semiconductor Products,” Proc. IEEE, vol. 87, no. 8, pp. 13291344, Aug. 1999.
[35] S. Shamshiri and K.T. (Tim) Cheng, “Yield and Cost Analysis for SpareEnhanced NetworkonChips,” UCSB technical report, http:/cadlab.ece.ucsb.edu, 2008.
[36] J.M. Carulli and T.J. Anderson, “The Impact of Multiple Failure Modes on Estimating Product Field Reliability,” IEEE Design & Test of Computers, vol. 23, no. 2, pp. 118126, Mar.Apr. 2006.
[37] V.V. Kumar and J. Lach, “IC Modeling for YieldAware Design with Variable Defect Rates,” Proc. Ann. Reliability and Maintainability Symp., pp. 489495, 2005.
[38] P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, and D. Burger, “OnChip Interconnection Networks of the TRIPS Chip,” IEEE Micro, vol. 27, no. 5, pp. 4150, Sept.Oct. 2007.
[39] S. Shamshiri and K.T. (Tim) Cheng, “ErrorLocalityAware Linear Coding to Correct Multibit Upsets in SRAMs,” Proc. IEEE Int'l Test Conf. (ITC), 2010.
[40] D. Rossi, P. Angelini, and C. Metra, “Configurable Error Control Scheme for NoC Signal Integrity,” Proc. IEEE 13th Int'l OnLine Testing Symp. (IOLTS), 2007.
[41] Q. Yu and P. Ampadu, “A Flexible Parallel Simulator for NetworksonChip with Error Control,” IEEE Trans. ComputerAided Design of Integrated Ciruits and Systems, vol. 29, no. 1, pp. 103116, Jan. 2010.
[42] J.A. Cunningham, “The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing,” IEEE Trans. Semiconductor Manufacturing, vol. 3, no. 2, pp. 6071, May 1990.
[43] I. Koren, Z. Koren, and C.H. Stapper, “A Unified NegativeBinomial Distribution for Yield Analysis of DefectTolerant Circuits” IEEE Trans. Computers, vol. 42, no. 6, pp. 724734, June 1993.
[44] T.H. Cormen, C.E. Leiserson, R.L. Rivest, and C. Stein, Introduction to Algorithms, second ed. MIT Press, 2001.
[45] T. Dumitras, S. Kerner, and R. Marculescu, “Towards OnChip FaultTolerant Communication,” Proc. Asia South Pacific Design Automation Conf., pp. 225232, 2003.
[46] B. Pittel, “On Spreading a Rumor,” SIAM J. Applied Math., vol. 47, no. 1, pp. 213223, Feb. 1987.