Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems
• C. Metra is with DEIS - University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy. E-mail: firstname.lastname@example.org.
• R. Galivanche is with Intel Corporation, 3600 Juliette Lane, Mail Stop SC12-604, Santa Clara, California 95070 USA, California. E-mail: Rajesh.email@example.com.
For information on obtaining reprints of this paper, please send e-mail to: firstname.lastname@example.org.
Cecilia Metra is a professor in electronics in the Department of Electronic, Computer Science and Systems (DEIS) of the University of Bologna. She is also affiliated with the Advanced Research Center on Electronic Systems for Information and Communication Technologies E. De Castro (ARCES) of the University of Bologna. She has been Visiting Scholar at the University of Washington, Seattle (USA) from 1998 to 2001, and Visiting Faculty Consultant for Intel Corporation, Santa Clara (CA) in 2002. She is the General Chair of the IEEE Int'l VLSI Test Symposium 2011, and she has been General Cochair of The IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems 2005 and 1999, of the IEEE Int'l On-Line Testing Symposium 2006 and of the IEEE Int'l On-Line Testing Workshop 2001, and Program Chair/Cochair of the IEEE Int'l VLSI Test Symposium 2009 and 2008, of the IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS) 2008, of The IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems 1998, of the IEEE Int'l On-Line Testing Symp. 2005, 2004, and 2003, and of the IEEE Int'l On-Line Testing Workshop 2002. She serves/served as Topic Chair and as Member of the Organizing Committee and/or Technical Program Committee of several international conferences. Her research interests are in the field of Design and Test of Integrated Digital Systems, Reliable and Error Resilient Systems, Fault Tolerance, On-Line Testing, Fault Modeling, Diagnosis and Debug, Emergent Technologies, Energy Harvesting and Security. She is Associate Editor in Chief of the IEEE Transactions on Computers, and a Member of the Editorial Board of the Journal of Electronic Testing: Theory and Applications and the International Journal of Highly Reliable Electronic System Design. She is a Senior Member and a Golden Core member of the IEEE Computer Society.
Rajesh Galivanche is a senior principal engineer in the Technology and Manufacturing Group at Intel. As the architect for DFT and Test Technology, Rajesh sets the strategy for research and development of Design-for-Test and HVM test technologies for Intel microprocessor and consumer SoC products. Rajesh also chaired the Intel wide task force on Logic Fault tolerance in Intel products. In these roles, he works closely with both the academia and the EDA industry in advancing the state-of -the-art in test and fault tolerant systems. Rajesh has published several papers in IEEE conference proceedings, two patents issued and two patent applications pending. He served as keynote speaker in many workshops in manufacturing test and online testing related workshops. Rajesh served on the Program Committees of IEEE VLSI Test Symposium, IEEE International Test Conference European Test Symposium in the past. Rajesh has an MS in electrical and computer engineering from the University of Iowa and is a senior member of IEEE.